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w WM8904 ultra low power codec for portable audio applications wolfson microelectronics plc to receive regular email updates, sign up at http://www.wolfsonmicro.com/ enews pre-production, september 2012, rev 3.3 copyright ? 2012 wolfson microelectronics plc description the WM8904 is a high performance ultra-low power stereo codec optimised for portable audio applications. the device features stereo ground-referenced headphone amplifiers using the wolfson ?c lass-w? amplifier techniques - incorporating an innovative dual-mode charge pump architecture - to optimise e fficiency and power consumption during playback. the ground-referenced headphone and line outputs eliminate ac coupling capacitors, and both outputs include common mode feedback paths to reject ground noise. control sequences for audio path setup can be pre-loaded and executed by an integrated control write sequencer to reduce software driver devel opment and minimise pops and clicks via wolfson?s silentswitch? technology. the analogue input stage can be configured for single ended or differential inputs. up to 3 stereo microphone or line inputs may be connected. the input impedance is constant with pga gain setting. a stereo digital microphone interface is provided, with a choice of two inputs. a dynamic range controller provides compression and level control to support a wide range of portable recording applications. anti-clip and quick release features offer good performance in the presence of loud impulsive noises. retune tm mobile 5-band parametric equaliser with fully programmable coefficients is in tegrated for optimization of speaker characteristics. programmable dynamic range control is also available fo r maximizing loudness, protecting speakers from clipping and pr eventing premature shutdown due to battery droop. common audio sampling frequencies are supported from a wide range of external clocks, either directly or generated via the fll. the WM8904 can operate directly from a single 1.8v switched supply. for optimal pow er consumption, the digital core can be operated from a 1.0v supply. features ? 3.0mw quiescent power consumption for dac to headphone playback ? dac snr 96db typical, thd -86db typical ? adc snr 91db typical, thd -80db typical ? 2.4mw quiescent power consumption for analogue bypass playback ? control write sequencer for pop minimised start-up and shutdown ? single register write for default start-up sequence ? integrated fll provides all necessary clocks - self-clocking modes allow processor to sleep - all standard sample rates from 8khz to 96khz ? stereo digital microphone input ? 3 single ended inputs per stereo channel ? 1 fully differential mic / line input per stereo channel ? digital dynamic range controller (compressor / limiter) ? digital sidetone mixing ? ground-referenced headphone driver ? ground-referenced line outputs ? 32-pin qfn package (4 x 4mm, 0.4mm pitch) ? 36-ball wlcsp package (2.6 x 2.5mm, 6 x 6 ball grid, 0.4mm pitch) applications ? portable multimedia players ? multimedia handsets ? handheld gaming ? wireless headsets ? mobile internet devices ? netbooks
WM8904 pre-production w pp, rev 3.3, september 2012 2 block diagram adcdat bclk / gpio4 dacdat lrclk cpgnd cpca cpcb mclk irq/gpio1 gpio2* vmidc agnd gpio3* 100nf 20 ? 100nf 20 ? 2.2f 2.2f 2.2f cpvdd 4.7f 100nf 20 ? 100nf 20 ? 4.7f 100nf 4.7f avdd dgnd dcvdd dbvdd bypass l bypass r dac l dac r decimation filters interpolation filters sda sclk 100nf 100nf
pre-production WM8904 w pp, rev 3.3, september 2012 3 table of contents descript ion ....................................................................................................... 1 ? featur es ............................................................................................................ 1 ? applications ..................................................................................................... 1 ? block diag ram ................................................................................................ 2 ? table of co ntents ......................................................................................... 3 ? audio signal path s diagram ...................................................................... 6 ? pin config uration .......................................................................................... 7 ? ordering info rmation .................................................................................. 8 ? pin descri ption ................................................................................................ 9 ? absolute maximu m ratings ...................................................................... 10 ? recommended operatin g condit ions ................................................... 10 ? electrical charact eristics ................................................................... 11 ? terminology ............................................................................................................ 11 ? common test co nditions .................................................................................... 11 ? input signal path ................................................................................................... 12 ? output signal path ............................................................................................... 16 ? bypass path .............................................................................................................. 18 ? charge pu mp ............................................................................................................ 18 ? fll ........................................................................................................................... ..... 18 ? other parameters ................................................................................................ 19 ? power consum ption .................................................................................... 21 ? common test co nditions .................................................................................... 21 ? power consumption measurements .............................................................. 21 ? signal timing re quiremen ts .................................................................... 25 ? common test co nditions .................................................................................... 25 ? master clock .......................................................................................................... 25 ? audio interface timing ........................................................................................ 26 ? master mode ................................................................................................................... ......................................... 26 ? slave mode ............................................................................................................................... ................................. 27 ? tdm mode ...................................................................................................................... ............................................. 28 ? control interface timing .................................................................................. 29 ? digital filter charact eristics .............................................................. 30 ? adc filter responses .......................................................................................... 31 ? adc high pass filte r responses ...................................................................... 31 ? dac filter responses .......................................................................................... 32 ? de-emphasis filte r responses ......................................................................... 33 ? device des cription ...................................................................................... 34 ? introduction ........................................................................................................... 34 ? analogue input si gnal path .............................................................................. 35 ? input pga enable .............................................................................................................. ...................................... 36 ? input pga co nfiguration........................................................................................................ ............................. 36 ? single-ended input ............................................................................................................ .................................... 38 ? differential line input ....................................................................................................... .................................. 38 ? differential microphone input ................................................................................................. ....................... 39 ? input pga gain control ........................................................................................................ ............................... 39 ? input pga common mode amplifier ............................................................................................... ................... 41 ? electret condenser mi crophone interface ............................................. 42 ? micbias control ............................................................................................................... ....................................... 42 ?
WM8904 pre-production w pp, rev 3.3, september 2012 4 micbias current detect ........................................................................................................ .............................. 43 ? micbias current detect filtering .............................................................................................. .................... 44 ? microphone hook switch detection .............................................................................................. ................ 46 ? digital microphon e interface .......................................................................... 47 ? analogue-to-digital converter (adc) ........................................................... 49 ? adc digital volume control .................................................................................................... .......................... 49 ? high pass filter .............................................................................................................. ........................................ 51 ? adc oversampling ratio (osr) .................................................................................................. ........................ 52 ? dynamic range co ntrol (drc) ........................................................................... 53 ? compression/limiting capabilities ............................................................................................. ..................... 53 ? gain limits ................................................................................................................... ............................................... 55 ? dynamic characteristics ....................................................................................................... ............................ 55 ? anti-clip control ............................................................................................................. ...................................... 56 ? quick release control ......................................................................................................... .............................. 57 ? gain smoothing ................................................................................................................ ....................................... 57 ? initialisation ................................................................................................................ ............................................ 58 ? retune tm mobile parametric equalizer (eq) ................................................ 59 ? default mode (5-band parametric eq) ........................................................................................... ................ 59 ? retune tm mobile mode ............................................................................................................................... ............ 60 ? eq filter characteristics ..................................................................................................... ............................ 60 ? digital mixing ........................................................................................................... 62 ? digital mixing paths .......................................................................................................... .................................... 62 ? dac interface volume boost .................................................................................................... ........................ 64 ? digital sidetone .............................................................................................................. ........................................ 64 ? digital-to-analogue converter (dac) ........................................................... 66 ? dac digital volume control .................................................................................................... .......................... 66 ? dac soft mute and soft un-mute ................................................................................................ ..................... 68 ? dac mono mix .................................................................................................................. .......................................... 69 ? dac de-emphasis ............................................................................................................................... ....................... 69 ? dac sloping stopband filter ................................................................................................... ......................... 70 ? dac oversampling ratio (osr) .................................................................................................. ........................ 70 ? output signal path ............................................................................................... 71 ? output signal paths enable .................................................................................................... .......................... 72 ? headphone / line output signal paths enable ................................................................................... ........ 72 ? output mux control ............................................................................................................ ................................. 76 ? output volume control.......................................................................................................... ............................ 76 ? analogue outputs ................................................................................................. 79 ? headphone outputs ? hpoutl and hpoutr ......................................................................................... .......... 79 ? line outputs ? lineoutl and lineoutr........................................................................................... ................. 79 ? external components for ground referenced outputs .................................................................... 80 ? reference voltages and master bias ........................................................... 81 ? analogue reference and master bias ............................................................................................ .............. 81 ? low power playback mode ....................................................................................................... ......................... 82 ? pop suppression control .................................................................................. 83 ? disabled input control ........................................................................................................ ............................... 83 ? charge pu mp ............................................................................................................ 84 ? dc servo .................................................................................................................... 8 5 ? dc servo enable and start-up .................................................................................................. ....................... 85 ? dc servo active modes ......................................................................................................... ............................... 88 ? dc servo readback ............................................................................................................. .................................. 90 ? digital audio interface ....................................................................................... 90 ? master and slave mode operation ............................................................................................... .................. 91 ? operation with tdm ............................................................................................................ ................................... 91 ? bclk frequency ................................................................................................................ ...................................... 92 ?
pre-production WM8904 w pp, rev 3.3, september 2012 5 audio data formats (normal mode) .............................................................................................. .................. 92 ? audio data formats (tdm mode).................................................................................................. ...................... 95 ? digital audio inte rface control..................................................................... 97 ? audio interface output tri-state .............................................................................................. ..................... 98 ? bclk and lrclk control ........................................................................................................ .............................. 98 ? companding .................................................................................................................... .......................................... 99 ? loopback ...................................................................................................................... ........................................... 101 ? digital pull-up and pull-down ................................................................................................. ....................... 101 ? clocking and sam ple rates ............................................................................. 102 ? sysclk control ................................................................................................................ .................................... 103 ? control interface clocking .................................................................................................... ...................... 104 ? clocking conf iguration ........................................................................................................ ........................... 104 ? adc / dac clock control ....................................................................................................... ............................ 105 ? opclk control ................................................................................................................. ..................................... 106 ? toclk control ................................................................................................................. ..................................... 106 ? adc / dac operation at 88.2k / 96k ............................................................................................ ....................... 107 ? frequency locked loop (fll) .......................................................................... 108 ? free-running fll clock ........................................................................................................ ............................. 112 ? gpio outputs from fll ......................................................................................................... .............................. 113 ? example fll calculation ....................................................................................................... ............................ 113 ? example fll settings .......................................................................................................... ................................ 114 ? general purpose input/ output (gpio) ......................................................... 115 ? irq/gpio1 ..................................................................................................................... .............................................. 115 ? gpio2 ......................................................................................................................... ................................................. 116 ? gpio3 ......................................................................................................................... ................................................. 116 ? bclk/gpio4 .................................................................................................................... ............................................ 117 ? interrupts .............................................................................................................. 118 ? using in1l and in1r as interrupt inputs ....................................................................................... ............... 122 ? control interface .............................................................................................. 123 ? control write sequencer ............................................................................... 125 ? initiating a sequence ......................................................................................................... ................................. 125 ? programming a sequence ........................................................................................................ ........................ 126 ? default sequences ............................................................................................................. ................................ 129 ? start-up sequence ............................................................................................................. ................................. 129 ? shutdown sequence ............................................................................................................. .............................. 131 ? power-on reset .................................................................................................... 133 ? quick start-up a nd shutdown ........................................................................ 135 ? quick start-up (default sequence) ............................................................................................. ................. 135 ? fast start-up from standby .................................................................................................... ....................... 135 ? quick shutdown (default sequence).............................................................................................. ............. 136 ? software reset a nd chip id ............................................................................. 137 ? register map ................................................................................................ 138 ? register bits by address ................................................................................. 142 ? applications in formation ...................................................................... 181 ? recommended external components ......................................................... 181 ? mic detection sequence us ing micbias current ..................................... 183 ? package dime nsions .................................................................................. 185 ? important no tice ....................................................................................... 187 ? address ................................................................................................................... 187 ? revision hi story ......................................................................................... 188 ?
WM8904 pre-production w pp, rev 3.3, september 2012 6 audio signal paths diagram
pre-production WM8904 w pp, rev 3.3, september 2012 7 pin configuration the WM8904 is supplied in a 32-pin qfn package or in a 36-ball csp format. the diagram below shows the 32-pin qfn configuration. a g n d l i n e o u t f b i n 2 r 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 1 2 3 4 5 6 7 8 1 6 1 5 1 4 1 3 1 2 1 1 1 0 9 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 i r q / g p i o 1 s c l k s d a d b v d d d g n d d c v d d c p v d d c p c a l i n e o u t r m i c v d d m i c b i a s v m i d c a v d d the following diagram shows the 36-ball csp configuration.
WM8904 pre-production w pp, rev 3.3, september 2012 8 ordering information device temperature range package moisture sensitivity level peak soldering temperature WM8904cgefl/v -40c to +85c 32-lead qfn (4x4x0.75mm, 0.4mm pitch, lead-free) msl3 260c WM8904cgefl/rv -40c to +85c 32-lead qfn (4x4x0.75mm, 0.4mm pi tch, lead-free, tape and reel) msl3 260c WM8904ecs/r -40c to +85c 36-ball w-csp (2.6x2.5x0.7mm, 6x6 ball grid, 0.4mm pitch, lead-free, tape and reel) msl1 260c note: qfn reel quantity = 3,500 w-csp reel quantity = 5,000
pre-production WM8904 w pp, rev 3.3, september 2012 9 pin description name wlcsp 66 qfn-32 type description in1l / dmicdat1 b3 27 analogue / digi tal input left channel input 1 / digital microphone data input 1 in2l a2 26 analogue input left channel input 2 in3l c3 n/a analogue input left channel input 3 in1r / dmicdat2 a1 25 analogue / digi tal input right channel input 1 / digital microphone data input 2 in2r b2 24 analogue input right channel input 2 in3r c2 n/a analogue input right channel input 3 micbias d1 20 analogue output microphone bias micvdd e1 19 supply microphone bias amp supply hpoutl e3 13 analogue output left headphone output (line or headphone output) hpoutr e2 15 analogue output right headphone output (line or headphone output) hpoutfb f3 14 analogue input headphone output ground loop noise rejection feedback lineoutl f2 16 analogue output left line output 1 (line output) lineoutr f1 18 analogue output right line output 1 (line output) lineoutfb d2 17 analogue input line output ground loop noise rejection feedback cpvdd e6 7 supply charge pump power supply cpgnd f6 9 supply charge pump ground cpca e5 8 analogue output charge pump flyback capacitor pin cpcb f5 10 analogue output charge pump flyback capacitor pin cpvoutp e4 11 analogue output c harge pump positive supply decoupling (powers hpoutl/r, lineoutl/r) cpvoutn f4 12 analogue output c harge pump negative supply decoupling (powers hpoutl/r, lineoutl/r) avdd b1 23 supply analogue power supply (powers analogue inputs, reference, adc, dac) agnd c1 22 supply analogue power return vmidc d3 21 midrail voltage decoupling capacitor dcvdd d5 6 supply digital core supply dbvdd c6 4 supply digital buffer supply (powers audio interface and control interface) dgnd d6 5 supply digital ground (return path for dcvdd and dbvdd) mclk a4 28 digital input master clock for codec bclk / gpio4 c4 29 digital input / out put audio interface bit clock / gpio4 lrclk a5 30 digital input / output audio interface left / right clock (common for adc and dac) dacdat a6 32 digital input dac digital audio data adcdat b5 31 digital output adc digital audio data sclk b6 2 digital input control interface clock input sda d4 3 digital input / output control interface data input / output gpio1 / irq c5 1 digital input / output gpio1 / interrupt gpio2 b4 n/a digital input / output gpio2 gpio3 a3 n/a digital input / output gpio3 gnd_paddle n/a 33 die paddle note: 1. it is recommended that the qfn ground paddle is connected to analogue ground on the application pcb.
WM8904 pre-production w pp, rev 3.3, september 2012 10 absolute maximum ratings absolute maximum ratings are stress ratings only. pe rmanent damage to the device ma y be caused by continuously operating at or beyond these limits. device functional operat ing limits and guaranteed performance specifications are given under electrical characteristics at the test conditions specified. esd sensitive device. this device is manufactured on a cmos process. it is therefore generically susceptible to damage from excessive static voltages. proper esd precautions must be taken during handling and storage of this device. wolfson tests its package types according to ipc/jedec j-std- 020b for moisture sensitivity to determine acceptable storage conditions prior to surface mount assembly. these levels are: msl1 = unlimited floor life at <30 ? c / 85% relative humidity. not normally stored in moisture barrier bag. msl2 = out of bag storage for 1 year at <30 ? c / 60% relative humidity. supplied in moisture barrier bag. msl3 = out of bag storage for 168 hours at <30 ? c / 60% relative humidity. supplied in moisture barrier bag. the moisture sensitivity level for each package type is specif ied in ordering information. condition min max avdd, dcvdd -0.3v +2.5v dbvdd, -0.3v +4.5v micvdd -0.3v +4.5v cpvdd -0.3v +2.2v hpoutl, hpoutr, lineoutl, lineoutr (cpvdd + 0.3v) * -1 cpvdd + 0.3v voltage range digital inputs dgnd -0.3v dbvdd +0.3v voltage range analogue inputs agnd -0.3v avdd +0.3v temperature range, t a -40 ? c +85 ? c storage temperature after soldering -65 ? c +150 ? c notes: 1. analogue and digital grounds must always be within 0.3v of each other. 2. all digital and analogue supplies are completely independent fr om each other; there is no restriction on power supply sequencing. 3. hpoutl, hpoutr, lineoutl, lineoutr are outputs, and should not normally become connected to dc levels. however, if the limits above are exceeded, then damage to the WM8904 may occur. recommended operating conditions parameter symbol min typ max unit digital supply range (core) dcvdd 0.95 1.0 1.98 v digital supply range (buffer) dbvdd 1.42 1.8 3.6 v analogue supplies range avdd 1.71 1.8 2.0 v charge pump supply range cpvdd 1.71 1.8 2.0 v microphone bias micvdd 1.71 2.5 3.6 v ground dgnd, agnd, cpgnd 0 v operating temperature (ambient) t a -40 +25 +85 ? c
pre-production WM8904 w pp, rev 3.3, september 2012 11 electrical characteristics terminology 1. signal-to-noise ratio (db) ? snr is the difference in level between a full scale output signal and the device output noise with no signal applied, measured over a bandwidth of 20h z to 20khz. this ratio is al so called idle channel noise. (no auto-zero or automute function is employed). 2. total harmonic distortion (db) ? thd is the difference in level between a 1khz full scale sinewave output signal and the first seven harmonics of the output signal. the amp litude of the fundamental frequency of the output signal is compared to the rms value of the next se ven harmonics and expressed as a ratio. 3. total harmonic distortion + noise (db) ? thd+n is the di fference in level between a 1khz full scale sine wave output signal and all noise and distortion products in the audio band. the amplitude of the fundamental reference frequency of the output signal is compared to the rms value of all other noise and distortion products and expressed as a ratio. 4. channel separation (db) ? is a measure of the coupli ng between left and right channels. a full scale signal is applied to the left channel only, the right channel amplitude is measured. then a full scale signal is applied to the right channel only and the left channel amplitude is measured. the wo rst case channel separati on is quoted as a ratio. 5. multi-path crosstalk (db) ? is the measured signal level in the idle path at the test signal frequency relative to the signal level at the output of the active path. the active path is configured and supplied wi th an appropriate input signal to drive a full scale output, with signal measured at the output of the specified idle path. 6. channel level matching (db) ? m easures the difference in gain betw een the left and the right channels. 7. power supply rejection ratio (db) ? psrr is a meas ure of ripple attenuation between the power supply pin and an output path. with the signal path idle, a small signal sine wa ve is summed onto the power supply rail, the amplitude of the sine wave is measured at the output port and expressed as a ratio. 8. all performance measurements carried out with 20khz aes17 low pass filter for distortion measurements, and an a-weighted filter for noise measurement. failure to use such a filter will result in higher thd and lower snr and dynamic range readings than are found in the electrical characteristics. t he low pass filter removes out of band noise; although it is not audible it may affect dynamic specification values. common test conditions unless otherwise stated, the following test conditions apply throughout the following sections: ? dcvdd = 1.0v ? dbvdd = 1.8v ? avdd = cpvdd =1.8v ? ambient temperature = +25c ? audio signal: 1khz sine wave, sampled at 48khz with 24-bit data resolution ? sysclk_src = 0 (system clock comes direct from mclk, not from fll). additional, specific test c onditions are given within t he relevant sections below.
WM8904 pre-production w pp, rev 3.3, september 2012 12 input signal path single-ended stereo line record - in1l+in1r pins to adc output test conditions: l_mode = r_mode = 00b (single ended) lin_vol = rin_vol = 00101b (0db) total signal path gain = 6db, incorporating 6db single-ended to differential conversion gain parameter symbol test conditions min typ max unit full scale input signal level (for adc 0dbfs). 0.50 -6 1.41 vrms dbv vpk-pk input resistance r in 9 12 k ? input capacitance c in 10 pf signal to noise ratio snr a-weighted adc_osr128 = 0 adc_128_osr_tst_ mode = 1 adc_biasx1p5 = 1 80 db a-weighted adc_osr128 = 1 adc_128_osr_tst_ mode = 0 adc_biasx1p5 = 0 80 90 total harmonic distortion + noise thd+n -7dbv input -78 -66 db channel separation 1khz signal, -7dbv 85 db 10khz signal, -7dbv 80 channel level matching 1khz signal, -7dbv +/-1 db power supply rejection ratio psrr 217hz, 100mvpk-pk 45 db 1khz, 100mv pk-pk 55
pre-production WM8904 w pp, rev 3.3, september 2012 13 differential stereo line record - in2l+in3l / in2r+in3r pins to adc output test conditions: l_mode = r_mode = 01b (differential line) lin_vol = rin_vol = 00101b (0db) total signal path gain = 0db parameter symbol test conditions min typ max unit line input full scale signal level applied to in2l or in2r (for adc 0dbfs output) 1.00 0 2.83 vrms dbv vpk-pk in3l, in3r input range mv input resistance r in 9 12 k ? input capacitance c in 10 pf signal to noise ratio snr a-weighted adc_osr128 = 0 adc_128_osr_tst_ mode = 1 adc_biasx1p5 = 1 80 db a-weighted best performance mode:: adc_osr128 = 1 adc_128_osr_tst_ mode = 0 adc_biasx1p5 = 0 81 91 total harmonic distortion + noise thd+n -1dbv input -78 -66 db common mode rejection ratio cmrr 1khz, 100mv pk-pk 60 db channel separation 1khz signal, -1dbv 85 db 10khz signal, -1dbv 80 channel level matching 1khz signal, -1dbv +/-1 db power supply rejection ratio psrr 217hz, 100mvpk-pk 55 db 1khz, 100mv pk-pk 55
WM8904 pre-production w pp, rev 3.3, september 2012 14 single-ended stereo record from analogue microphones - in2l / in2r pins to adc output test conditions: l_mode = r_mode = 00b (single ended) lin_vol = rin_vol = 11111b (+28.3db) total signal path gain = +34.3db, incorporating 6db single-ended to differential conversion gain parameter symbol test conditions min typ max unit single-ended mic input full-scale signal level (for adc 0dbfs output) 0.019 -34.3 0.055 vrms dbv vpk-pk input resistance r in 9 12 k ? input capacitance c in 10 pf signal to noise ratio snr a-weighted adc_osr128 = 0 adc_128_osr_tst_ mode = 1 adc_biasx1p5 = 1 65 db a-weighted best performance mode:: adc_osr128 = 1 adc_128_osr_tst_ mode = 0 adc_biasx1p5 = 0 73 total harmonic distortion + noise thd+n -35.3dbv input -69 db channel level matching 1khz signal, -35.3dbv +/-3 db power supply rejection ratio psrr 217hz, 100mvpk-pk 45 db 1khz, 100mv pk-pk 55
pre-production WM8904 w pp, rev 3.3, september 2012 15 differential stereo record from analogue microphones - in1l+in2l / in1r+in2r pins to adc output test conditions: l_mode = r_mode = 10b (differential mic) lin_vol = rin_vol = 00111b (+30db) total signal path gain = +30db parameter symbol test conditions min typ max unit differential mic input full scale signal level in1l-in2l / in1r-in2r (for adc 0dbfs output) 0.032 -30 0.089 vrms dbv vpk-pk input resistance rin 100 120 k ? input capacitance cin 10 pf signal to noise ratio snr a-weighted adc_osr128 = 0 adc_128_osr_tst _mode = 1 adc_biasx1p5 = 1 68 db a-weighted best performance mode:: adc_osr128 = 1 adc_128_osr_tst _mode = 0 adc_biasx1p5 = 0 67 77 total harmonic distortion + noise thd+n -31dbv input -75 -65 db common mode rejection ratio cmrr 1khz, 100mvpk-pk 60 db channel separation 1khz signal, -31dbv 85 db 10khz signal, -31dbv 80 channel level matching 1khz signal, -31dbv +/-1 db psrr (referred to input) psrr 217hz, 100mvpk-pk 50 db 1khz, 100mv pk-pk 50 pga and microphone boost parameter test conditions min typ max unit minimum pga gain setting l_mode/r_mode= 00b or 01b -1.55 db l_mode/r_mode= 10b +12 maximum pga gain setting l_mode/r_mode= 00b or 01b +28.28 db l_mode/r_mode= 10b +30 single-ended to differential conversion gain l_mode/r_mode= 00b +6 db pga gain accuracy l_mode/r_mode= 00b gain -1.5 to +6.7db -1 +1 db l_mode/r_mode= 00b gain +7.5 to +28.3db -1.5 +1.5 l_mode/r_mode= 1x gain +12 to +24db -1 +1 l_mode/r_mode= 1x gain +27 to +30db -1.5 +1.5 mute attenuation all modes of operation 100 db equivalent input noise l_mode/r_mode= 00b or 01b 30 214 vrms nv/ hz
WM8904 pre-production w pp, rev 3.3, september 2012 16 output signal path high performance stereo playback to headphones - dac input to hpoutl+hpoutr pins with 15 ? load test conditions: hpoutl_vol = hpoutr_vol = 111001b (0db) low power playback mode disabled. (see table 49 for details; note that low power playback mode is disabled by default.) parameter symbol test conditions min typ max unit output power (per channel) p o 1% thd r load = 30 ? 28 0.92 -0.76 mw vrms dbv 1% thd r load = 15 ? 32 0.69 -3.19 mw vrms dbv dc offset dc servo enabled, calibration complete. -1.5 +1.5 mv signal to noise ratio snr a-weighted 90 96 db total harmonic distortion + noise thd+n r l =30 ? ; p o =2mw -91 db r l =30 ? ; p o =20mw -84 r l =15 ? ; p o =2mw -87 -80 r l =15 ? ; p o =20mw -85 channel separation 1khz signal, 0dbfs 100 db 10khz signal, 0dbfs 90 channel level matching 1khz signal, 0dbfs +/-1 db power supply rejection ratio psrr 217hz, 100mvpk-pk 75 db 1khz, 100mv pk-pk 70 low power stereo playback to headphones - dac input to hpoutl+hpoutr pins with 15 ? load test conditions: hpoutl_vol = hpoutr_vol = 111001b (0db) low power playback mode enabled (see table 48 for details) parameter symbol test conditions min typ max unit output power (per channel) p o 1% thd r load = 30 ? 27 0.90 -0.92 mw vrms dbv 1% thd r load = 15 ? 30 0.67 -3.5 mw vrms dbv signal to noise ratio snr a-weighted 95 db total harmonic distortion + noise thd+n r l =30 ? ; p o =2mw -91 db r l =30 ? ; p o =20mw -83 r l =15 ? ; p o =2mw -87 r l =15 ? ; p o =20mw -80
pre-production WM8904 w pp, rev 3.3, september 2012 17 high performance stereo playback to line-out - dac input to lineoutl+lineoutr pins with 10k ? / 50pf load test conditions: lineoutl_vol = lineoutr_vol = 111001b (0db) low power playback mode disabled. (see table 49 for details; note that low power playback mode is disabled by default.) parameter symbol test conditions min typ max unit full scale output signal level dac 0dbfs output at 0db volume 1.0 0 2.83 vrms dbv vpk-pk dc offset dc servo enabled. calibration complete. -1.5 +1.5 mv signal to noise ratio snr a-weighted 90 96 db total harmonic distortion + noise thd+n 10k ? load -85 -70 db channel separation 1khz signal, 0dbfs 100 db 10khz signal, 0dbfs 90 channel level matching 1khz signal, 0dbfs +/-1 db power supply rejection ratio psrr 217hz, 100mvpk-pk 62 db 1khz, 100mv pk-pk 62 low power stereo playback to line-out - dac input to lineoutl+lineoutr pins with 10k ? / 50pf load test conditions: lineoutl_vol = lineoutr_vol = 111001b (0db), low power playback mode enabled (see table 48 for details) parameter symbol test conditions min typ max unit full scale output signal level dac 0dbfs output at 0db volume 1.0 0 2.83 vrms dbv vpk-pk signal to noise ratio snr a-weighted 95 db total harmonic distortion + noise thd+n 10k ? load -82 db output pgas (hp, line) parameter test conditions min typ max unit minimum pga gain setting -57 db maximum pga gain setting 6 db pga gain step size 1 db pga gain accuracy +6db to -40db -1.5 +1.5 db pga gain accuracy -40db to -57db -1 +1 db mute attenuation hpoutl/r 85 db lineoutl/r 85 db
WM8904 pre-production w pp, rev 3.3, september 2012 18 bypass path differential stereo line input to stereo line output - in2l-in3l / in2r-in3r pins to lineoutl+lineoutr pins with 10k ? / 50pf load test conditions: l_mode = r_mode = 01b (differential line) lin_vol = rin_vol = 00101b (0db) lineoutl_vol = lineoutr_vol = 111001b (0db) total signal path gain = 0db parameter symbol test conditions min typ max unit full scale output signal level 1.0 0 2.83 vrms dbv vpk-pk signal to noise ratio snr a-weighted 90 100 dbv total harmonic distortion + noise thd+n -1dbv input -92 -85 dbv channel separation 1khz signal, -1dbv 90 db 10khz signal, -1dbv 80 channel level matching 1khz signal, -1dbv +/-1 db power supply rejection ratio psrr 217hz, 100mv pk-pk 45 db charge pump parameter test conditions min typ max unit start-up time 260 ? s cpca normal mode cpvdd v low power mode cpvdd/2 v cpcb normal mode -cpvdd v low power mode -cpvdd/2 v external component requirements to achieve specified headphone output power and performance ? flyback capacitor (between cpca and cpcb) at 2v 1 2.2 ? f cpvoutn capacitor at 2v 2 2.2 ? f cpvoutp capacitor at 2v 2 2.2 ? f fll parameter symbol test conditions min typ max unit input frequency f ref fll_clk_ref_div = 00 0.032 13.5 mhz fll_clk_ref_div = 01 0.064 27 mhz lock time 2 ms free-running mode start-up time vmid enabled 100 ? s free-running mode frequency accuracy reference supplied initially +/-10 % no reference provided +/-30 %
pre-production WM8904 w pp, rev 3.3, september 2012 19 other parameters vmid reference parameter test conditions min typ max unit midrail reference voltage (vmidc pin) -3% avdd/2 +3% v charge up time (from fully discharged to 10% below vmid) external capacitor 4.7 ? f 890 s microphone bias (for analogue electret condenser microphones) additional test conditions: micbias_ena=1, all parameters measured at the micbias pin parameter symbol test conditions min typ max unit bias voltage. note: 7/6 and 9/10 are available only if micvdd > avdd. note: 3/2 and 4/3 are available only if micvdd 2.5v. v micbias micvdd = 2.5v 3ma load current, micbias_sel = 1xx -10% 3/2 x avdd +10% v micbias_sel = 011 -10% 4/3 x avdd +10% micbias_sel = 010 -10% 7/6 x avdd +10% micbias_sel = 001 -10% 10/9 x avdd +10% micbias_sel = 000 -10% 9/10 avdd +10% drop out voltage between micvdd and micbias 200 mv maximum source current i micbias 4 ma noise spectral density at 1khz 19 nv/ hz power supply rejection ratio micvdd to micbias psrr 1khz, 100mv pk-pk micvdd = 1.71 v 67 db 20khz, 100mv pk-pk micvdd = 1.71 v 76 1khz, 100mv pk-pk micvdd = 2.5 v 88 20khz, 100mv pk-pk micvdd = 2.5 v 84 1khz, 100mv pk-pk micvdd = 3.6 v 61 20khz, 100mv pk-pk micvdd = 3.6 v 70 power supply rejection ratio micvdd and avdd to micbias psrr 1khz, 100mv pk-pk avdd = micvdd = 1.8 v 54 db 20khz, 100mv pk-pk avdd = micvdd = 1.8 v 79 micbias current detect function (see note 1) current detect threshold (microphone insertion) micdet_thr = 00 80 ? a current detect threshold (microphone removal) 60 delay time for current detect interrupt t det 3.2 ms micbias short circuit (hook switch) detect function (see note 1) short circuit detect threshold (button press) micshort_thr = 00 600 ? a short circuit detect threshold (button release) 400 minimum delay time for short circuit detect interrupt t short 47 ms note 1 : if avdd ? 1.8, current threshold values s hould be multiplied by (avdd/1.8)
WM8904 pre-production w pp, rev 3.3, september 2012 20 digital inputs / outputs parameter symbol test conditions min typ max unit input high level (digital input) v ih 0.7 ? dbvdd v input low level (digital input) v il 0.3 ? dbvdd v input high level (analogue / digital input) v ih 0.7 ? avdd v input low level (analogue / digital input) v il 0.3 ? avdd v output high level v oh i oh = +1ma 0.9 ? dbvdd v output low level v ol i ol = -1ma 0.1 ? dbvdd v multi-path crosstalk test conditions: input path = in1l/in1r to adc, 0db gain output path = dac to hpoutl/hpoutr, 0db gain fs = 48khz parameter symbol test conditions min typ max unit dac to adc crosstalk 1khz signal, 0dbfs -45 db adc to dac crosstalk 1khz signal, -7dbv -60 db
pre-production WM8904 w pp, rev 3.3, september 2012 21 power consumption the WM8904 power consumption is dependent on many parameters. most significantly, it depends on supply voltages, sample rates, mode of operation, and output loading. the power consumption on each s upply rail varies approximately with the square of the voltage. power consumption is greater at fast sample rates than at slower ones. when the digital audio interface is operating in master mode, the dbvdd cu rrent is significantly greater than in slave mode. (note also that power savings can be made by usi ng mclk as the bclk source in slave mode.) the output load conditions (impedance, capacitance and inductance) can al so impact significantly on the device power consumption. common test conditions unless otherwise stated, the following test conditions apply throughout the following sections: ? ambient temperature = +25c ? audio signal = quiescent (zero amplitude) ? sample rate = 48khz ? mclk = 12.288mhz ? audio interface mode = slave (lrclk_dir=0, bclk_dir=0) ? sysclk_src = 0 (system clock comes direct from mclk, not from fll) additional, variant test conditions are quoted within the relevant sections below. where applicable, power dissipated in the headphone or line loads is included. power consumption measurements single-ended stereo line record - in1l/r, in2l/r or in3l/r pins to adc output. test conditions: l_mode = r_mode = 00b (single ended) lin_vol = rin_vol = 00101 = +0.0 db adc_osr128 = 0 (64*fs), adc_128_osr_tst_mode = 1, adc_biasx1p5 = 1 micbias = disabled variant test conditions avdd dcvdd dbvdd cpvdd micvdd total v ma v ma v ma v ma v ma mw 48khz sample rate 1.80 4.38 1.00 0.80 1.80 0.02 1.80 0.01 1.80 0.01 8.72 8khz sample rate 1.80 4.25 1.00 0.14 1.80 0.00 1.80 0.01 1.80 0.01 7.81 48khz -6dbv sine wave 1.80 4.41 1.00 0.80 1.80 0.03 1.80 0.01 1.80 0.01 8.81 differential stereo record from analogue microphones - in1l/r, in2l/r or in3l/r pins to adc out. test conditions: l_mode = r_mode = 10b (differential mic) lin_vol = rin_vol = 00111 = +30.0 db adc_osr128 = 0 (64*fs), adc_128_osr_tst_mode = 1, adc_biasx1p5 = 1 micbias_ena = 1, micbias_sel = 000, no load connected to micbias variant test conditions avdd dcvdd dbvdd cpvdd micvdd total v ma v ma v ma v ma v ma mw 48khz sample rate 1.80 4.38 1.00 0.80 1.80 0.02 1.80 0.01 1.80 0.01 8.73 8khz sample rate 1.80 4.25 1.00 0.14 1.80 0.00 1.80 0.01 1.80 0.01 7.81 48khz -30dbv sine wave 1.80 4.39 1.00 0.81 1.80 0.03 1.80 0.01 1.80 0.01 8.78
WM8904 pre-production w pp, rev 3.3, september 2012 22 high performance stereo playback to headphones - dac input to hpoutl+hpoutr pins with 30 ? load. test conditions: vmid_res = 01 (for normal operation) cp_dyn_pwr = 1 (class-w, charge pump controlled by real-time audio level) low power playback mode disabled. (see table 49 for details; note that low power playback mode is disabled by default.) variant test conditions avdd dcvdd dbvdd cpvdd micvdd total v ma v ma v ma v ma v ma mw 48khz sample rate 1.80 1.69 1.00 0.76 1.80 0.00 1.80 0.31 2.50 0.01 4.38 8khz sample rate 1.80 1.69 1.00 0.18 1.80 0.00 1.80 0.31 2.50 0.01 3.80 48khz, po = 0.1mw/channel 1khz sine wave 0dbfs hpout_vol= -25db dac_vol= 0db 1.80 1.71 1.00 0.77 1.80 0.00 1.80 1.99 2.50 0.01 7.45 48khz, po = 1mw/channel 1khz sine wave 0dbfs hpout_vol= -15db dac_vol= 0db 1.80 1.73 1.00 0.77 1.80 0.00 1.80 5.61 2.50 0.01 13.99 48khz sample rate, master mode, fll enabled, mclk input frequency = 13mhz 1.80 1.82 1.00 1.05 1.80 0.73 1.80 0.30 2.50 0.01 6.18 48khz sample rate, master mode, fll enabled, mclk input frequency = 32.768khz 1.80 1.83 1.00 0.94 1.80 0.76 1.80 0.29 2.50 0.01 6.14 low power stereo playback to headphones - dac input to hpoutl+hpoutr pins with 30 ? load. test conditions: vmid_res = 01 (for normal operation) cp_dyn_pwr = 1 (class-w, charge pump controlled by real-time audio level) low power playback mode enabled (see table 48 for details) sysclk = 6.144mhz, clk_sys_rate = 0001b (for 128 fs clocking) variant test conditions avdd dcvdd dbvdd cpvdd micvdd total v ma v ma v ma v ma v ma mw 48khz sample rate 1.80 0.99 1.00 0.61 1.80 0.00 1.80 0.31 2.50 0.01 2.98 48khz, po = 0.1mw/channel 1khz sine wave 0dbfs hpout_vol= -25db dac_vol= 0db 1.80 1.02 1.00 0.62 1.80 0.00 1.80 1.68 2.50 0.01 5.51 48khz, po = 1mw/channel 1khz sine wave 0dbfs hpout_vol= -15db dac_vol= 0db 1.80 1.04 1.00 0.62 1.80 0.00 1.80 5.23 2.50 0.01 11.93
pre-production WM8904 w pp, rev 3.3, september 2012 23 high performance stereo playback to line-out - dac input to lineoutl+lineoutr or hpoutl+hpoutr pins with 10k ? / 50pf load test conditions: vmid_res = 01 (for normal operation) cp_dyn_pwr = 1 (class-w, charge pump controlled by real-time audio level) low power playback mode disabled. (see table 49 for details; note that low power playback mode is disabled by default.) variant test conditions avdd dcvdd dbvdd cpvdd micvdd total v ma v ma v ma v ma v ma mw 48khz sample rate 1.80 1.67 1.00 0.76 1.80 0.00 1.80 0.36 2.50 0.01 4.43 8khz sample rate 1.80 1.67 1.00 0.18 1.80 0.00 1.80 0.36 2.50 0.01 3.86 48khz, po = 0dbfs 1khz sine wave 1.80 1.78 1.00 0.77 1.80 0.00 1.80 2.27 2.50 0.01 8.09 low power stereo playback to line-out - dac input to lineoutl+lineoutr or hpoutl+hpoutr pins with 10k ? / 50pf load test conditions: vmid_res = 01 (for normal operation) cp_dyn_pwr = 1 (class-w, charge pump controlled by real-time audio level) low power playback mode enabled (see table 48 for details) sysclk = 6.144mhz, clk_sys_rate = 0001b (for 128 fs clocking) variant test conditions avdd dcvdd dbvdd cpvdd micvdd total v ma v ma v ma v ma v ma mw 48khz sample rate 1.80 0.99 1.00 0.61 1.80 0.00 1.80 0.22 2.50 0.01 2.81 48khz, po = 0dbfs 1khz sine wave 1.80 1.04 1.00 0.62 1.80 0.00 1.80 1.77 2.50 0.01 5.70
WM8904 pre-production w pp, rev 3.3, september 2012 24 stereo analogue bypass to headphones - in1l/r, in2l/r or in3l/r pins to hpoutl+hpoutr pins with 30 ? load. test conditions: lin_vol = rin_vol = 00101 = +0.0 db mclk = 11.2896mhz digital audio interface disabled note that the analogue bypass configuration does not benefit from the class w dynamic control. variant test conditions avdd dcvdd dbvdd cpvdd micvdd total v ma v ma v ma v ma v ma mw quiescent hpoutvol = 000000 (-57db) 1.8 1.24 1 0.11 1.8 0.00 1.8 0.26 2.5 0.01 2.82 po = 0.1mw/channel 1khz sine wave hpoutvol = 100000 (-25db) 1.8 1.29 1 0.11 1.8 0.00 1.8 2.05 2.5 0.01 6.13 po = 1mw/channel 1khz sine wave hpoutvol = 101010 (-15db) 1.8 1.30 1 0.11 1.8 0.00 1.8 5.86 2.5 0.01 13.02 stereo analogue bypass to line-out - in1l/r, in2l/r or in3l/r pins to lineoutl+lineoutr pins with 30 ? load. test conditions: lin_vol = rin_vol = 00101 = +0.0 db mclk = 11.2896mhz digital audio interface disabled note that the analogue bypass configuration does not benefit from the class w dynamic control. variant test conditions avdd dcvdd dbvdd cpvdd micvdd total v ma v ma v ma v ma v ma mw quiescent lineoutvol = 000000 (-57db) 1.8 1.04 1.0 0.15 1.8 0. 00 1.8 0.21 1.8 0.01 2.41 quiescent lineoutvol = 101011 (-14db) 1.8 1.04 1.0 0.15 1.8 0. 00 1.8 0.63 1.8 0.01 3.18 quiescent lineoutvol = 111001 (0db) 1.8 1.04 1.0 0.15 1.8 0. 00 1.8 1.25 1.8 0.01 4.28 off note: dc servo calibration is retained in this state as long as dcvdd is supplied. this allows fast, pop suppressed start-up from th e off state. variant test conditions avdd dcvdd dbvdd cpvdd micvdd total v ma v ma v ma v ma v ma mw off (default settings) no clocks applied 1.8 0.01 1 0.00 1.8 0.00 1.8 0.01 2.5 0.01 0.04 off (default settings) dacdat, mclk, bclk, and lrclk applied 1.8 0.01 1 0.02 1.8 0.00 1.8 0.01 2.5 0.01 0.06
pre-production WM8904 w pp, rev 3.3, september 2012 25 signal timing requirements common test conditions unless otherwise stated, the following test conditions apply throughout the following sections: ? ambient temperature = +25c ? dcvdd = 1.0v ? dbvdd = avdd = cpvdd = 1.8v ? dgnd = agnd = cpgnd = 0v additional, specific test c onditions are given within t he relevant sections below. master clock figure 1 master clock timing master clock timing parameter symbol test conditions min typ max unit mclk cycle time t mclky mclk_div=1 40 ns mclk_div=0 80 ns mclk duty cycle t mclkds 60:40 40:60
WM8904 pre-production w pp, rev 3.3, september 2012 26 audio interface timing master mode bclk (output) adcdat lrclk (output) t dl dacdat t dda t dht t dst figure 2 audio interface timing ? master mode test conditions dcvdd = 1.0v, avdd = dbvdd = cpvdd = 1.8v, dgnd=agnd=cpgnd =0v, t a = +25 o c, master mode, fs=48khz, mclk=256fs, 24-bit data, unless otherwise stated. parameter symbol min typ max unit audio interface timing - master mode lrclk propagation delay from bclk falling edge t dl 20 ns adcdat propagation delay from bclk falling edge t dda 20 ns dacdat setup time to bclk rising edge t dst 20 ns dacdat hold time from bclk rising edge t dht 10 ns
pre-production WM8904 w pp, rev 3.3, september 2012 27 slave mode bclk (input) lrclk (input) adcdat (output) dacdat (input) t ds t dd t dh t lrh t lrsu t bch t bcl t bcy figure 3 audio interface timing ? slave mode test conditions dcvdd = 1.0v, avdd = dbvdd = cpvdd = 1.8v, dgnd=agnd=cpgnd =0v, t a = +25 o c, slave mode, fs=48khz, mclk=256fs, 24-bit data, unless otherwise stated. parameter symbol min typ max unit audio interface timing - slave mode bclk cycle time t bcy 50 ns bclk pulse width high t bch 20 ns bclk pulse width low t bcl 20 ns lrclk set-up time to bclk rising edge t lrsu 20 ns lrclk hold time from bclk rising edge t lrh 10 ns dacdat hold time from bclk rising edge t dh 10 ns adcdat propagation delay from bclk falling edge t dd 20 ns dacdat set-up time to bclk rising edge t ds 20 ns note: bclk period must always be greater than or equal to mclk period.
WM8904 pre-production w pp, rev 3.3, september 2012 28 tdm mode in tdm mode, it is important that two adc devices do not attempt to drive the adcdat pin simultaneously. the timing of the WM8904 adcdat tri-stating at the start and end of the data transmission is described below. figure 4 audio interface timing - tdm mode test conditions avdd = cpvdd = 1.8v , dgnd=agnd=cpgnd= =0v, t a = +25 o c, master mode, fs=48khz, mclk=256fs, 24-bit data, unless otherwise stated. parameter conditions min typ max unit audio data timing information adcdat setup time from bclk falling edge dcvdd =2.0v dbvdd = 3.6v 5 ns dcvdd = 1.08v dbvdd = 1.62v 15 ns adcdat release time from bclk falling edge dcvdd = 2.0v dbvdd = 3.6v 5 ns dcvdd = 1.08v dbvdd = 1.62v 15 ns
pre-production WM8904 w pp, rev 3.3, september 2012 29 control interface timing figure 5 control interface timing test conditions dcvdd = 1.0v, avdd = dbvdd = cpvdd = 1.8v, dgnd=agnd=cpgnd =0v, t a =+25 o c, slave mode, fs=48khz, mclk = 256fs, 24-bit data, unless otherwise stated. parameter symbol min typ max unit sclk frequency 400 khz sclk low pulse-width t 1 1300 ns sclk high pulse-width t 2 600 ns hold time (start condition) t 3 600 ns setup time (start condition) t 4 600 ns data setup time t 5 100 ns sda, sclk rise time t 6 300 ns sda, sclk fall time t 7 300 ns setup time (stop condition) t 8 600 ns data hold time t 9 900 ns pulse width of spikes that will be suppressed t ps 0 5 ns
WM8904 pre-production w pp, rev 3.3, september 2012 30 digital filter characteristics parameter test conditions min typ max unit adc filter passband +/- 0.05db 0 0.454 fs -6db 0.5 fs passband ripple +/- 0.05 db stopband 0.546s stopband attenuation f > 0.546 fs -60 db dac normal filter passband +/- 0.05db 0 0.454 fs -6db 0.5 fs passband ripple 0.454 fs +/- 0.03 db stopband 0.546 fs stopband attenuation f > 0.546 fs -50 db dac sloping stopband filter passband +/- 0.03db 0 0.25 fs +/- 1db 0.25 fs 0.454 fs -6db 0.5 fs passband ripple 0.25 fs +/- 0.03 db stopband 1 0.546 fs 0.7 fs stopband 1 attenuation f > 0.546 fs -60 db stopband 2 0.7 fs 1.4 fs stopband 2 attenuation f > 0.7 fs -85 db stopband 3 1.4 fs stopband 3 attenuation f > 1.4 fs -55 db dac filters adc filters mode group delay mode group delay normal 16.5 / fs normal 16.5 / fs sloping stopband 18 / fs terminology 1. stop band attenuation (db) ? the degree to which the frequency spectrum is attenuated (outside audio band) 2. pass-band ripple ? any variation of t he frequency response in the pass-band region
pre-production WM8904 w pp, rev 3.3, september 2012 31 adc filter responses figure 6 adc digital filter frequency response figure 7 adc digital filter ripple adc high pass filter responses ma gnitude( db) 1 2.6923 7.2484 19.515 52.54 141.45 38 0.83 1.0253k 2.7605k 7.432k 20.009k -11.736 -10.562 -9.3883 -8.2145 -7.0407 -5.8669 -4.6931 -3.5193 -2.3455 -1.1717 2.1246m hpf_response.res magnitude(db) hpf_response2.res magnitude(db) hpf_response2.res#1 magnitude(db) 2 5.0248 12.624 31.716 79.683 200.19 502.96 1.2636k 3.1747k 7.9761k 20.039k -83.352 -75.017 -66.682 -58.347 -50.012 -41.677 -33.342 -25.007 -16.672 -8.3373 -2.3338m figure 8 adc digital high pass filter frequency response (48khz, hi-fi mode, adc_hpf_cut[1:0]=00) figure 9 adc digital high pass filter ripple (48khz, voice mode, adc_hpf_cut=01, 10 and 11)
WM8904 pre-production w pp, rev 3.3, september 2012 32 dac filter responses magnitude(db) -0.005 0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 frequency (fs) figure 10 dac digital filter frequency response; (normal mode); sample rate > 24khz figure 11 dac digital filter ripple (normal mode) magnitude(db) -0.5 -0.45 -0.4 -0.35 -0.3 -0.25 -0.2 -0.15 -0.1 -0.05 0 0.05 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 frequency (fs) figure 12 dac digital filter frequency response; (sloping stopband mode); sample rate <= 24khz figure 13 dac digital filter ripple (sloping stopband mode)
pre-production WM8904 w pp, rev 3.3, september 2012 33 de-emphasis filter responses magnitude(db) -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0 5000 10000 15000 20000 frequency (hz) magnitude(db) -0.15 -0.1 -0.05 0 0.05 0.1 0.15 0.2 0.25 0.3 0 2000 4000 6000 8000 10000 12000 14000 16000 18000 frequency (hz) figure 14 de-emphasis digital filter response (32khz) figure 15 de-emphasis error (32khz) magnitude(db) -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 0 5000 10000 15000 20000 25000 frequency (hz) magnitude(db) -0.1 -0.05 0 0.05 0.1 0.15 0.2 0 5000 10000 15000 20000 25000 frequency (hz) figure 16 de-emphasis digital filter response ( 44.1khz) figure 17 de-emphasis error (44.1khz) magnitude(db) -12 -10 -8 -6 -4 -2 0 0 5000 10000 15000 20000 25000 30000 frequency (hz) magnitude(db) -0.15 -0.1 -0.05 0 0.05 0.1 0.15 0 5000 10000 15000 20000 25000 30000 frequency (hz) figure 18 de-emphasis digital filter response (48khz) figure 19 de-emphasis error (48khz)
WM8904 pre-production w pp, rev 3.3, september 2012 34 device description introduction the WM8904 is a high performance ultra-low pow er stereo codec optimised for portable audio applications. flexible analogue interfaces and powerful digital signal processing (dsp) make it ideal for small portable devices. the WM8904 supports up to 6 analogue audio inputs. one pair of single-ended or differential microphone/line inputs is selected as the adc input s ource. an integrated bias reference is provided to power standard electret microphones. a two-channel digital microphone interface is also s upported, with direct input to the dsp core bypassing the adcs. one pair of ground-reference class-w headphone output s is provided; these are powered from an integrated charge pump, enabling high quality, power efficient headphone playback without any requirement for dc blocking capacitors. a dc servo circuit is available fo r dc offset correction, thereby suppressing pops and reduci ng power consumption. two line outputs are provided; these are also capable of driving ear speakers and stereo headsets. ground loop feedback is available on the headphone outputs and the line outputs, providing reje ction of noise on the ground connections. all outputs use wolfson silentswitch? te chnology for pop and click suppression. the stereo adcs and dacs are of hi-fi quality, usi ng a 24-bit low-order oversampling architecture to deliver optimum performance. a flexible clocki ng arrangement supports mixed adc and dac sample rates, whilst an integrated ultra-low power fll prov ides additional flexibility. a high pass filter is available in the adc path for removing dc offs ets and suppressing low frequency noise such as mechanical vibration and wind noise. a digital mixi ng path from the adc to the dac provides a sidetone of enhanced quality during voice calls. dac so ft mute and un-mute is available for pop-free music playback. the integrated dynamic range controller (drc) and retunetm mobile 5-band parametric equaliser (eq) provide further processing capability of t he digital audio paths. the drc provides compression and signal level control to improve the handling of unpredictable signal levels. ?anti-clip? and ?quick release? algorithms improve intelligibility in the pr esence of transients and impulsive noises. the eq provides the capability to tailor the audio path a ccording to the frequency characteristics of an earpiece or loudspeaker, and/or a ccording to user preferences. the WM8904 has a highly flexible digital audio interf ace, supporting a number of protocols, including i2s, dsp, msb-first left/right justified, and can operate in master or slave modes. pcm operation is supported in the dsp mode. a-law and ? -law companding are also supported. time division multiplexing (tdm) is available to allow multiple devices to stream data simultaneously on the same bus, saving space and power. the system clock sysclk provides clocking for the adcs, dacs, dsp core, digital audio interface and other circuits. sysclk can be derived directly from the mclk pin or via an integrated fll, providing flexibility to support a wide range of cl ocking schemes. typical portable system mclk frequencies, and sample rates from 8khz to 48khz are all supported. the clocking circuits are configured automatically from the sample rate (fs) and from the sysclk / fs ratio. the integrated fll can be used to generate sysclk from a wide variety of different reference sources and frequencies. the fll can accept a wi de range of reference frequencies, which may be high frequency (e.g. 13mhz) or low frequency (eg. 32.768k hz). the fll is tolerant of jitter and may be used to generate a stable sysclk from a less stable input signal. the integrated fll can be used as a free-running oscillator, enabling autonomous clocking of the charge pump and dc servo if required. the WM8904 uses a standard 2-wire control interface, providing full software control of all features, together with device register readback. an int egrated control write sequencer enables automatic scheduling of control sequences; co mmonly-used signal configurations may be selected using ready- programmed sequences, including time-optimised c ontrol of the WM8904 pop suppression features. it is an ideal partner for a wide range of industr y standard microprocessors, controllers and dsps. unused circuitry can be di sabled under software control, in order to save power; low leakage currents enable extended standby/off time in portable battery-powered applications.
pre-production WM8904 w pp, rev 3.3, september 2012 35 up to 4 gpio pins may be configured for miscellaneous input/output functions such as button/accessory detect inputs, or for clock, syst em status, or programmable logic level output for control of additional external ci rcuitry. interrupt logic, stat us readback and de-bouncing options are supported within this functionality. analogue input signal path the WM8904 has six analogue input pi ns, which may be used to suppor t connections to multiple microphone or line input sources. the input multip lexer on the left and right channels can be used to select different configurations for each of t he input sources. the anal ogue input paths can support line and microphone inputs, in single-ended and different ial modes. the input stage can also provide common mode noise rejection in some configurations. two of the six analogue input pi ns have dual functionality and c an be used as digital microphone inputs. (see the ?digital microphone interface? section for details.) the left and right analogue input channels are routed to the analogue to digita l converters (adcs). there is also a bypass path for each channel, enabling the signal to be routed directly to the output multiplexers and pgas. the WM8904 input signal paths and control registers are illustrated in figure 20. figure 20 block diagram for input signal path
WM8904 pre-production w pp, rev 3.3, september 2012 36 input pga enable the input pgas (programmable gain amplifiers) and multiplexers are enabled using register bits inl_ena and inr_ena, as shown in table 1. register address bit label default description r12 (0ch) power management 0 1 inl_ena 0 left input pga enable 0 = disabled 1 = enabled 0 inr_ena 0 right input pga enable 0 = disabled 1 = enabled table 1 input pga enable to enable the input pgas, the reference voltage vm id and the bias current must also be enabled. see reference voltages and master bias for det ails of the associated controls vmid_res and bias_ena. input pga configuration the analogue input channels can each be configured in three different modes, which are as follows: ? single-ended mode (inverting) ? differential line mode ? differential mic mode the mode is selected by the l_mode and r_mo de fields for the left and right channels respectively. the input pins are selected using the l_ip_sel_n and l_ip_sel_p fields for the left channel and the r_ip_sel_n and r_ip_sel_p fo r the right channel. in single-ended mode, l_ip_sel_n alone determines the left input pin, and the r_ip_sel_n determines the right input pin. the three modes are illustrated in figure 21, figure 22 and figure 23. it should be noted that the available gain and input impedance varies between configurati ons (see also ?electrical characteristics?). the input impedance is constant with pga gain setting. the input pga modes are selected and configured us ing the register fields described in table 2 below.
pre-production WM8904 w pp, rev 3.3, september 2012 37 register address bit label default description r46 (2eh) analogue left input 1 5:4 l_ip_sel_n [1:0] 00 in single-ended or differential line modes, this field selects the input pin for the inverting side of the left input path. in differential mic mode, this field selects the input pin for the non- inverting side of the left input path. 00 = in1l 01 = in2l 1x = in3l 3:2 l_ip_sel_p [1:0] 01 in single-ended or differential line modes, this field selects the input pin for the non-inverting side of the left input path. in differential mic mode, this field selects the input pin for the inverting side of the left input path. 00 = in1l 01 = in2l 1x = in3l 1:0 l_mode [1:0] 00 sets the mode for the left analogue input: 00 = single-ended 01 = differential line 10 = differential mic 11 = reserved r47 (2fh) analogue right input 1 5:4 r_ip_sel_n [1:0] 00 in single-ended or differential line modes, this field selects the input pin for the inverting side of the right input path. in differential mic mode, this field selects the input pin for the non- inverting side of the right input path. 00 = in1r 01 = in2r 1x = in3r 3:2 r_ip_sel_p [1:0] 01 in single-ended or differential line modes, this field selects the input pin for the non-inverting side of the right input path. in differential mic mode, this field selects the input pin for the inverting side of the right input path. 00 = in1r 01 = in2r 1x = in3r 1:0 r_mode [1:0] 00 sets the mode for the right analogue input: 00 = single-ended 01 = differential line 10 = differential mic 11 = reserved table 2 input pga mode selection
WM8904 pre-production w pp, rev 3.3, september 2012 38 single-ended input the single-ended pga configuration is illustrated in figure 21 for the left channel. the available gain in this mode is from -1.57db to +28.5db in non-linear steps. the input to the adc is phase inverted with respect to the selected input pin. di fferent input pins can be selected in the same mode by altering the l_ip_sel_n field. the equivalent configuration is also avail able on the right channel; this can be selected independently of the left channel mode. figure 21 single ended mode differential line input the differential line pga configuration is illustra ted in figure 22 for the left channel. the available gain in this mode is from -1.57db to +28.5db in non-linear steps. the input to the adc is in phase with the input pin selected by l_ip_sel_p. the input to the adc is phase inverted with respect to the input pin selected by l_ip_sel_n. as an option, common mode noise rejection can be prov ided in this pga configuration, as illustrated in figure 22. this is enabled using the register bits defined in table 5. the equivalent configuration is also avail able on the right channel; this can be selected independently of the left channel mode. figure 22 differential line mode
pre-production WM8904 w pp, rev 3.3, september 2012 39 differential microphone input the differential mic pga configuration is illustra ted in figure 23 for the left channel. the available gain in this mode is from +12db to +30db in 3db linear steps. the input to the adc is in phase with the input pin selected by l_ip_sel_n. the input to the adc is phase inverted with respect to the input pin selected by l_ip_sel_p. note that the inverting input pin is selected using l_ip_sel_p and the non-inverting input pin is selected using l_ip_sel_n. this is not the same as for the differential line mode. the equivalent configuration is also avail able on the right channel; this can be selected independently of the left channel mode. figure 23 differential microphone mode input pga gain control the volume control gain for the left and ri ght channels be independently controlled using the lin_vol and rin_vol register fields as descri bed in table 3. the available gain range varies according to the selected pga mode as detailed in table 4. note that the value ?00000? must not be used in differential mic mode, as the pga will not function correctly under this setting. in single- ended mode (l_mode / r_mode = 00b), the conversion from single-ended to differential within the WM8904 adds a further 6db of gain to the signal path. each input channel can be independently muted using linmute and rinmute. it is recommended to not adjust the gain dynamica lly whilst the signal path is enabled; the signal should be muted at the input or output stage prior to adjusting the volume control. register address bit label default description r44 (2ch) analogue left input 0 7 linmute 1 left input pga mute 0 = not muted 1 = muted 4:0 lin_vol [4:0] 00101 left input pga volume (see table 4 for volume range) r45 (2dh) analogue right input 0 7 rinmute 1 right input pga mute 0 = not muted 1 = muted 4:0 rin_vol [4:0] 00101 right input pga volume (see table 4 for volume range) table 3 input pga volume control
WM8904 pre-production w pp, rev 3.3, september 2012 40 lin_vol [4:0], rin_vol [4:0] gain ? single-ended mode / differential line mode gain ? differential mic mode 00000 -1.5 db not valid 00001 -1.3 db +12 db 00010 -1.0 db +15 db 00011 -0.7 db +18 db 00100 -0.3 db +21 db 00101 0.0 db +24 db 00110 +0.3 db +27 db 00111 +0.7 db +30 db 01000 +1.0 db +30 db 01001 +1.4 db +30 db 01010 +1.8 db +30 db 01011 +2.3 db +30 db 01100 +2.7 db +30 db 01101 +3.2 db +30 db 01110 +3.7 db +30 db 01111 +4.2 db +30 db 10000 +4.8 db +30 db 10001 +5.4 db +30 db 10010 +6.0 db +30 db 10011 +6.7 db +30 db 10100 +7.5 db +30 db 10101 +8.3 db +30 db 10110 +9.2 db +30 db 10111 +10.2 db +30 db 11000 +11.4 db +30 db 11001 +12.7 db +30 db 11010 +14.3 db +30 db 11011 +16.2 db +30 db 11100 +19.2 db +30 db 11101 +22.3 db +30 db 11110 +25.2 db +30 db 11111 +28.3 db +30 db table 4 input pga volume range
pre-production WM8904 w pp, rev 3.3, september 2012 41 input pga common mode amplifier in differential line mode only, a common mode am plifier can be enabled as part of the input pga circuit. this feature provides approximately 20db reduction in common mode noise on the differential input, which can reduce problematic interference. since the adc has di fferential signal inputs, it has an inherent immunity to common mode noise (see ?elect rical characteristics?) however, the presence of common mode noise can limit the usable si gnal range of the adc path; enabling the common mode amplifier can solve this issue. it should be noted that the common mode amplifier consumes additional power and can also add its own noise to the input signal. fo r these reasons, it is recommended that the common mode amplifier is only enabled if there is a known s ource of common mode interference. the common mode amplifier is controlled by the inl_cm_ena and inr_cm_ena fields as described in table 5. although the common mode amplifier may be enabled regardless of the input pga mode, its function is only effective in the differential line mode configuration. register address bit label default description r46 (2eh) analogue left input 1 6 inl_cm_ena 1 left input pga common mode rejection enable 0 = disabled 1 = enabled (only available for l_mode=01 ? differential line) r47 (2fh) analogue right input 1 6 inr_cm_ena 1 right input pga common mode rejection enable 0 = disabled 1 = enabled (only available for r_mode=01 ? differential line) table 5 common mode amplifier enable
WM8904 pre-production w pp, rev 3.3, september 2012 42 electret condenser microphone interface electret condenser microphones may be connected as single-ended or differential inputs to the input pgas described in the ?analogue input signal path ? section. the WM8904 provides a low-noise reference voltage (micbias) suitable fo r biasing electret condenser microphones. micbias control the micbias reference is provided on the micbias pin. this reference voltage is enabled by setting the micbias_ena register bit. the micbias output voltage is selected using the mi cbias_sel register. this register selects the output voltage as a ratio of avdd; the actual output voltage scales with avdd. the micbias output is powered from the micvdd s upply pin, and uses vmid (ie. avdd/2) as a reference, as illustrated in figure 24. in all ca ses, micvdd must be at least 200mv greater than the required micbias output voltage. under the default setting of micbias_sel, the mi cvdd supply may be connected directly to avdd. for other settings of micbias_sel, (ie. for hi gher micbias voltages), the micvdd supply must be greater than avdd. the micbias generator is illustrated in in figure 24. the associated control registers are defined in table 6. figure 24 micbias generator register address bit label default description r6 (06h) mic bias control 0 0 micbias_ena 0 micbias enable 0 = disabled 1 = enabled r7 (07h) mic bias control 1 2:0 micbias_sel [2:0] 000 selects micbias voltage 000 = 9/10 x avdd (1.6v) 001 = 10/9 x avdd (2.0v) 010 = 7/6 x avdd (2.1v) 011 = 4/3 x avdd (2.4v) 100 to 111 = 3/2 x avdd (2.7v) note that the voltage scales with avdd. the value quoted in brackets is correct for avdd=1.8v. table 6 micbias control
pre-production WM8904 w pp, rev 3.3, september 2012 43 micbias current detect a micbias current detect function is provided for ex ternal accessory detection. this is provided in order to detect the insertion/removal of a mi crophone or the pressing/releasing of the microphone ?hook? switch; these events will cause a signific ant change in micbias current flow, which can be detected and used to generate a signal to the host processor. the micbias current detect function is enabled by setting the micdet_ena register bit. when this function is enabled, two current thresholds can be defined, using the micdet_thr and micshort_thr registers. when a change in micbias current which crosses either threshold is detected, then an interrupt event can be generated. in a typical application, accessory insertion would be detected when the micbias current exceeds micdet_thr, and microphone hookswitch operation would be detected when the micbias current exceeds micshort_thr. the current detect threshold functi ons are both inputs to the interr upt control circuit and can be used to trigger an interrupt event when either threshold is crossed. both events can also be indicated as an output on a gpio pin - see ?general purpose input/output (gpio)?. the current detect thresholds are enabled and contro lled using the registers described in table 7. performance parameters for this circ uit block can be found in the ?electrical characteristics? section. hysteresis and filtering is also provided in the bot h current detect circuits to improve reliability in conditions where ac current spikes are present due to ambient noise conditions. these features are described in the following section. further guidanc e on the usage of the micbias current monitoring features is also described in the following pages. register address bit label default description r6 (06h) mic bias control 0 6:4 micdet_thr [2:0] 000 micbias current detect threshold (avdd = 1.8v) 000 = 0.070ma 001 = 0.260ma 010 = 0.450ma 011 = 0.640ma 100 = 0.830ma 101 = 1.020ma 110 = 1.210ma 111 = 1.400ma note that the value scales with avdd. the value quoted is correct for avdd=1.8v. 3:2 micshort_thr [1:0] 00 micbias short circuit threshold (avdd = 1.8v) 00 = 0.520ma 01 = 0.880ma 10 = 1.240ma 11 = 1.600ma note that the value scales with avdd. the value quoted is correct for avdd=1.8v. 1 micdet_ena 0 micbias current and short circuit detect enable 0 = disabled 1 = enabled table 7 micbias current detect
WM8904 pre-production w pp, rev 3.3, september 2012 44 micbias current detect filtering the function of the filtering is to ensure that ac current spikes caused by ambient noise conditions near the microphone do not lead to incorrect signalling of the microphone insertion/removal status or the microphone hookswitch status. hysteresis on the current thresholds is provided; this means that a different current threshold is used to detect microphone insertion and microphone removal. si milarly, a different current threshold is used to detect hookswitch press and hookswtich release. digital filtering of the hookswitch status ensures that the micbias short ci rcuit detection event is only signalled if the micshort_thr threshol d condition has been met for 10 consecutive measurements. in a typical application, microphone insertion woul d be detected when the micbias current exceeds the current detect threshold set by micdet_thr. when the mic_det_eint_pol interrupt polarity bi t is set to 0, then microphone insertion detection will cause the mic_det_eint interrupt status register to be set. for detection of microphone removal, the mic_det_ eint_pol bit should be set to 1. when the mic_det_eint_pol interrupt polarity bit is se t to 1, then microphone removal detection will cause the mic_det_eint interrupt status register to be set. the detection of these events is bandwidth limited for best noise rejection, and is subject to detection delay time t det , as specified in the ?electrical characte ristics?. provided that the micdet_thr field has been set appropriately, each insertion or removal event is guaranteed to be detected within the delay time t det . it is likely that the microphone socket contacts will have mechanical ?bounce? when a microphone is inserted or removed, and hence the resultant contro l signal will not be a clean logic level transition. since t det has a range of values, it is possible that the interrupt will be generated before the mechanical ?bounce? has ceased. h ence after a mic insertion or removal has been detected, a time delay should be applied before re-c onfiguring the mic_det_eint_pol bit. the maximum possible mechanical bounce times for mic insertion and removal must be understood by the software programmer. utilising a gpio pin to monitor the steady stat e of the microphone detecti on function does not change the timing of the detection mechanism , so there will also be a delay t det before the signal changes state. it may be desirable to implement de-bounce in the host processor when monitoring the state of the gpio signal. microphone hook switch operation is detected when t he micbias current exceeds the short circuit detect threshold set by micshort_thr. using the digital filtering, the hook switch detection event is only signalled if the micshort_thr thres hold condition has been me t for 10 consecutive measurements. when the mic_shrt_eint_pol interrupt polarity bi t is set to 0, then hook switch operation will cause the mic_shrt_eint interrupt status register to be set. for detection of microphone removal, the mic_shrt _eint_pol bit should be set to 1. when the mic_shrt_eint_pol interrupt polarity bit is set to 1, then hook switch release will cause the mic_shrt_eint interrupt status register to be set. the hook switch detection measurement frequency and the detection delay time t short are detailed in the ?electrical characteristics? section. the WM8904 interrupt function is described in the ?int errupts? section. example control sequences for configuring the interrupts functions for micbi as current detection events are described in the ?applications information? section.
pre-production WM8904 w pp, rev 3.3, september 2012 45 a clock is required for the digital filtering func tion, and the dc servo must also be running. this requires: ? mclk is present or the fll is selected as the sysclk source in free-running mode ? clk_sys_ena = 1 ? dcs_ena_chan_n is enabled (where n = 0, 1, 2 or 3) any micbias current detect event (accessory insert ion/removal or hookswitch press/release) which happens while one or more of the clocking criteria is not satisfied (for example during a low power mode where the cpu has disabled mclk) will still be detected, but only after the clocking conditions are met. an example is illustrated in figure 25, where the mic is inserted while mclk is stopped. figure 25 micbias detection events without mclk
WM8904 pre-production w pp, rev 3.3, september 2012 46 microphone hook switch detection the possibility of spurious hook switch interrupts due to ambient noise condi tions can be removed by careful understanding of microphone behaviour under extr emely high sound pressure levels or during mechanical shock, and by correct selection of the micb ias resistor value; these factors will affect the level of the micbias ac current spikes. in applications where where the current detect thres hold is close to the level of the current spikes, the probability of false detections is reduced by t he hysteresis and digital filtering described above. note that the filtering algorithm provides only limited rejection of very high current spikes at frequencies less than or equal to the hook switch detect measurement frequency, or at frequencies equal to harmonics of the hook switch detect measurement frequency. the micbias hook switch detection filtering is illustrated in figure 26. example control sequences for configuring the interrupts functions for micb ias current detection events are described in the ?applications information? section. figure 26 micbias hook switch detection filtering
pre-production WM8904 w pp, rev 3.3, september 2012 47 digital microphone interface the WM8904 supports a stereo digital microphone interf ace. this may be provided on dmicdat1 or on dmicdat2, as selected by the dmic_src r egister bit. the analogue signal path from the selected input pin must be disabled when using the digital microphone interface; this is achieved by configuring or disabling the associated input pga. the two-channel audio data is multiplexed on the selected input pin. the associated clock, dmicclk, is provided on a gpio pin. the digital microphone input is selected as input by setting the dmic_ena bit. when the digital microphone input is selected, the adc is bypassed. the digital microphone interface configur ation is illustrated in figure 27. note that care must be taken to ensure that the re spective digital logic levels of the microphone are compatible with the digital input thresholds of the WM8904. the digital input thresholds are referenced to dbvdd, as defined in ?electrical characteristics?. it is recommended to power the digital microphones from dbvdd. figure 27 digital microphone interface when any gpio pin is configured as dmic clock output, the WM8904 outputs a clock, which supports digital microphone operation at the adc sa mpling rate. the adc and record path filters must be enabled and the adc sampling rate must be set in order to ensure correct operation of all dsp functions associated with the digital mi crophone. volume control for the digital microphone interface signals is provided us ing the adc volume control. see ?analogue-to-digital converter (adc)? for det ails of the adc enable and volume control functions. see ?general purpose i nput/output (gpio)? for details of configuring the dmicclk output. see ?clocking and sample rates? for details of the sample rate control. when the dmic_ena bit is set, then the in1l/dmi cdat1 or in1r/dmicdat2 pin is used as the digital microphone input dmicdat. up to two mi crophones can share each pi n; the two microphones are interleaved as illustrated in figure 28.
WM8904 pre-production w pp, rev 3.3, september 2012 48 the digital microphone interface requires that mic1 (left channel) transmits a data bit each time that dmicclk is high, and mic2 (right channel) trans mits when dmicclk is low. the WM8904 samples the digital microphone data in the middle of each dmicclk clock phase. each microphone must tri- state its data output when the other microphone is transmitting. figure 28 digital microphone interface timing the digital microphone interface control fields are described in table 8. register address bit label default description r39 (27h) digital microphone 0 12 dmic_ena 0 enables digital microphone mode 0 = audio dsp input is from adc 1 = audio dsp input is from digital microphone interface when dmic_ena = 0, the digital microphone clock (dmicclk) is held low. 11 dmic_src 0 selects digital microphone data input pin 0 = in1l/dmicdat1 1 = in1r/dmicdat2 table 8 digital microphone interface control
pre-production WM8904 w pp, rev 3.3, september 2012 49 analogue-to-digital converter (adc) the WM8904 uses stereo 24-bit, 128x oversampled si gma-delta adcs. the use of multi-bit feedback and high oversampling rates reduces the effects of jitter and high frequency noise. an oversample rate of 64x can also be supported - see ?clocking and sample rates? for details. the adc full scale input level is proportional to avdd - see ?electrical characteristics?. any input signal greater than full scale may overload the adc and cause distortion. the adcs are enabled by the adcl_e na and adcr_ena register bits. register address bit label default description r18 (12h) power management (6) 1 adcl_ena 0 left adc enable 0 = adc disabled 1 = adc enabled 0 adcr_ena 0 right adc enable 0 = adc disabled 1 = adc enabled table 9 adc enable control adc digital volume control the output of the adcs can be digitally amplif ied or attenuated over a range from -71.625db to +17.625db in 0.375db steps. the volume of each c hannel can be controlled s eparately. the gain for a given eight-bit code is detailed in table 11. the adc_vu bit controls the loading of digital volu me control data. when adc_vu is set to 0, the adcl_vol or adcr_vol control data will be loaded into the respective control register, but will not actually change the digital gain setting. both left and right gain settings are updated when a 1 is written to adc_vu. this makes it possible to update the gain of both channels simultaneously. register address bit label default description r36 (24h) adc digital volume left 8 adc_vu 0 adc volume update writing a 1 to this bit will cause left and right adc volume to be updated simultaneously 7:0 adcl_vol [7:0] 1100_0000 (0db) left adc digital volume 00h = mute 01h = -71.625db 02h = -71.250db ? (0.375db steps) c0h = 0db ? (0.375db steps) efh to ffh = +17.625db (see table 11 for volume range) r37 (25h) adc digital volume right 8 adc_vu 0 adc volume update writing a 1 to this bit will cause left and right adc volume to be updated simultaneously 7:0 adcr_vol [7:0] 1100_0000 (0db) right adc digital volume 00h = mute 01h = -71.625db 02h = -71.250db ? (0.375db steps) c0h = 0db ? (0.375db steps) efh to ffh = +17.625db (see table 11 for volume range) table 10 adc digital volume control
WM8904 pre-production w pp, rev 3.3, september 2012 50 adcl_vol or adcr_vol volume (db) adcl_vol or adcr_vol volume (db) a dcl_vol or adcr_vol volume (db) a dcl_vol or adcr_vol volume (db) 0h mute 40h -48.000 80h -24.000 c0h 0.000 1h -71.625 41h -47.625 81h -23.625 c1h 0.375 2h -71.250 42h -47.250 82h -23.250 c2h 0.750 3h -70.875 43h -46.875 83h -22.875 c3h 1.125 4h -70.500 44h -46.500 84h -22.500 c4h 1.500 5h -70.125 45h -46.125 85h -22.125 c5h 1.875 6h -69.750 46h -45.750 86h -21.750 c6h 2.250 7h -69.375 47h -45.375 87h -21.375 c7h 2.625 8h -69.000 48h -45.000 88h -21.000 c8h 3.000 9h -68.625 49h -44.625 89h -20.625 c9h 3.375 ah -68.250 4ah -44.250 8ah -20.250 cah 3.750 bh -67.875 4bh -43.875 8bh -19.875 cbh 4.125 ch -67.500 4ch -43.500 8ch -19.500 cch 4.500 dh -67.125 4dh -43.125 8dh -19.125 cdh 4.875 eh -66.750 4eh -42.750 8eh -18.750 ceh 5.250 fh -66.375 4fh -42.375 8fh -18.375 cfh 5.625 10h -66.000 50h -42.000 90h -18.000 d0h 6.000 11h -65.625 51h -41.625 91h -17.625 d1h 6.375 12h -65.250 52h -41.250 92h -17.250 d2h 6.750 13h -64.875 53h -40.875 93h -16.875 d3h 7.125 14h -64.500 54h -40.500 94h -16.500 d4h 7.500 15h -64.125 55h -40.125 95h -16.125 d5h 7.875 16h -63.750 56h -39.750 96h -15.750 d6h 8.250 17h -63.375 57h -39.375 97h -15.375 d7h 8.625 18h -63.000 58h -39.000 98h -15.000 d8h 9.000 19h -62.625 59h -38.625 99h -14.625 d9h 9.375 1ah -62.250 5ah -38.250 9ah -14.250 dah 9.750 1bh -61.875 5bh -37.875 9bh -13.875 dbh 10.125 1ch -61.500 5ch -37.500 9ch -13.500 dch 10.500 1dh -61.125 5dh -37.125 9dh -13.125 ddh 10.875 1eh -60.750 5eh -36.750 9eh -12.750 deh 11.250 1fh -60.375 5fh -36.375 9fh -12.375 dfh 11.625 20h -60.000 60h -36.000 a0h -12.000 e0h 12.000 21h -59.625 61h -35.625 a1h -11.625 e1h 12.375 22h -59.250 62h -35.250 a2h -11.250 e2h 12.750 23h -58.875 63h -34.875 a3h -10.875 e3h 13.125 24h -58.500 64h -34.500 a4h -10.500 e4h 13.500 25h -58.125 65h -34.125 a5h -10.125 e5h 13.875 26h -57.750 66h -33.750 a6h -9.750 e6h 14.250 27h -57.375 67h -33.375 a7h -9.375 e7h 14.625 28h -57.000 68h -33.000 a8h -9.000 e8h 15.000 29h -56.625 69h -32.625 a9h -8.625 e9h 15.375 2ah -56.250 6ah -32.250 aah -8.250 eah 15.750 2bh -55.875 6bh -31.875 abh -7.875 ebh 16.125 2ch -55.500 6ch -31.500 ach -7.500 ech 16.500 2dh -55.125 6dh -31.125 adh -7.125 edh 16.875 2eh -54.750 6eh -30.750 aeh -6.750 eeh 17.250 2fh -54.375 6fh -30.375 afh -6.375 efh 17.625 30h -54.000 70h -30.000 b0h -6.000 f0h 17.625 31h -53.625 71h -29.625 b1h -5.625 f1h 17.625 32h -53.250 72h -29.250 b2h -5.250 f2h 17.625 33h -52.875 73h -28.875 b3h -4.875 f3h 17.625 34h -52.500 74h -28.500 b4h -4.500 f4h 17.625 35h -52.125 75h -28.125 b5h -4.125 f5h 17.625 36h -51.750 76h -27.750 b6h -3.750 f6h 17.625 37h -51.375 77h -27.375 b7h -3.375 f7h 17.625 38h -51.000 78h -27.000 b8h -3.000 f8h 17.625 39h -50.625 79h -26.625 b9h -2.625 f9h 17.625 3ah -50.250 7ah -26.250 bah -2.250 fah 17.625 3bh -49.875 7bh -25.875 bbh -1.875 fbh 17.625 3ch -49.500 7ch -25.500 bch -1.500 fch 17.625 3dh -49.125 7dh -25.125 bdh -1.125 fdh 17.625 3eh -48.750 7eh -24.750 beh -0.750 feh 17.625 3fh -48.375 7fh -24.375 bfh -0.375 ffh 17.625 table 11 adc digital volume range
pre-production WM8904 w pp, rev 3.3, september 2012 51 high pass filter a digital high pass filter is applied by default to t he adc path to remove dc offsets. this filter can also be programmed to remove low frequency noise in voice applications (e.g. wind noise or mechanical vibration). this filter is controlled using the adc_hpf and adc_ hpf_cut register bits. in hi-fi mode the high pass filter is optimised for removing dc offsets without degrading the bass response and has a cut-off frequenc y of 3.7hz at fs=44.1khz. in voice mode the high pass filter is optimised for voice communication and it is recommended to program the cut-off frequency below 300hz (e.g. adc_hpf_cut=11 at fs=8khz or adc_hpf_cut=10 at fs=16khz). register address bit label default description r38 (26h) adc digital 0 6:5 adc_hpf_c ut [1:0] 00 adc digital high pass filter cut-off frequency (fc) 00 = hi-fi mode (fc=4hz at fs=48khz) 01 = voice mode 1 (fc=127hz at fs=16khz) 10 = voice mode 2 (fc=130hz at fs=8khz) 11 = voice mode 3 (fc=267hz at fs=8khz) (note: fc scales with sample rate. see table 13 for cut-off frequencies at all supported sample rates) 4 adc_hpf 1 adc digital high pass filter enable 0 = disabled 1 = enabled table 12 adc digital 0 register sample frequency (khz) cut-off frequency (hz) adc_hpf_cut =00 adc_hpf_cut =01 adc_hpf_cut =10 adc_hpf_cut =11 8.000 0.7 64 130 267 11.025 0.9 88 178 367 16.000 1.3 127 258 532 22.050 1.9 175 354 733 24.000 2.0 190 386 798 32.000 2.7 253 514 1063 44.100 3.7 348 707 1464 48.000 4.0 379 770 1594 table 13 adc high pass filter cut-off frequencies the high pass filter characteristics are shown in the ?digital filter char acteristics? section.
WM8904 pre-production w pp, rev 3.3, september 2012 52 adc oversampling ratio (osr) the adc oversampling rate is programmable to allow power consumption versus audio performance trade-offs. the default oversampling rate is high for best performance; using the lower osr setting reduces adc power consumption. to ensure specified adc performanc e, the adc bias control bits in register r198 must be set correctly, depending on the adc_osr128 value, as described in table 14. register address bit label default description r10 (0ah) analogue adc 0 0 adc_osr128 1 adc oversampling ratio 0 = low power (64 x fs) 1 = high performance (128 x fs) r198 (c6h) adc test 0 2 adc_128_osr _tst_mode 0 adc bias control (1) set this bit to 1 in adc 64fs mode (adc_osr128 = 0). set this bit to 0 in adc 128fs mode (adc_osr128 = 1). 0 adc_biasx1p 5 0 adc bias control (2) set this bit to 1 in adc 64fs mode (adc_osr128 = 0). set this bit to 0 in adc 128fs mode (adc_osr128 = 1). table 14 adc oversampling ratio
pre-production WM8904 w pp, rev 3.3, september 2012 53 dynamic range control (drc) the dynamic range controller (drc) is a circuit whic h can be enabled in the digital data path of either the adcs or the dacs. the function of the drc is to adjust the signal gain in conditions where the input amplitude is unknown or varies over a wide range, e.g. when recording from microphones built into a handheld system. the drc can apply compressi on and automatic level control to the signal path. it incorporates ?anti-clip? and ?quick release? features for handling transients in order to improve intelligibility in the presence of loud impulsive noises. the drc is enabled by drc_ena, as shown in table 15. it can be enabled in the adc digital path or in the dac digital path, under the control of t he drc_dac_path register bit. note that the drc can be active in only one of these paths at any time. register address bit label default description r40 (28h) drc control 0 15 drc_ena 0 drc enable 0 = disabled 1 = enabled 14 drc_dac_pat h 0 drc path select 0 = adc path 1 = dac path table 15 drc enable compression/limiting capabilities the drc supports two different compression regions, separated by a ?knee? at input amplitude t. for signals above the knee, the compression slope drc_hi _comp applies; for signals below the knee, the compression slope drc_lo_comp applies. the overall drc compression characteristic in ?steady state? (i.e. where the input amplitude is near- constant) is illustrated in figure 29. drc_knee_ip (y0) 0db d r c _ h i _ c o m p d r c _ l o _ c o m p drc input amplitude (db) drc output amplitude (db) drc_knee_op ?knee? figure 29 drc compression characteristic the slope of the drc response is determi ned by register fields drc_hi_comp and drc_lo_comp respectively. a slope of 1 indicates c onstant gain in this region. a slope less than 1 represents compression (i.e. a change in input am plitude produces only a smaller change in output amplitude). a slope of 0 indicates that the target output amplitude is the same across a range of input amplitudes; this is infinite compression.
WM8904 pre-production w pp, rev 3.3, september 2012 54 the ?knee? in figure 29 is represented by register fields drc_knee_ip and drc_knee_op. parameter y0, the output level for a 0db input, is not specified directly, but can be calculated from the other parameters, using the equation the drc compression parameters are defined in table 16. register address bit label default description r43 (2bh) drc control 3 10:5 drc_knee_ip [5:0] 00_0000 input signal at the compressor 'knee'. 000000 = 0db 000001 = -0.75db 000010 = -1.5db ? (-0.75db steps) 111100 = -45db 111101 to 111111 = reserved 4:0 drc_knee_op [4:0] 0_0000 output signal at the compressor 'knee'. 00000 = 0db 00001 = -0.75db 00010 = -1.5db ? (-0.75db steps) 11110 = -22.5db 11111 = reserved r42 (2ah) drc control 2 5:3 drc_hi_comp [2:0] 000 compressor slope (upper region) 000 = 1 (no compression) 001 = 1/2 010 = 1/4 011 = 1/8 100 = 1/16 101 = 0 110 to 111 = reserved 2:0 drc_lo_comp [2:0] 000 compressor slope (lower region) 000 = 1 (no compression) 001 = 1/2 010 = 1/4 011 = 1/8 100 = 0 101 to 111 = reserved table 16 drc compression control
pre-production WM8904 w pp, rev 3.3, september 2012 55 gain limits the minimum and maximum gain applied by the drc is set by register fields drc_mingain and drc_maxgain. these limits can be used to alter t he drc response from that illustrated in figure 29. if the range between maximum and minimum gain is reduced, then the extent of the dynamic range control is reduced. the maximum gain pr events quiet signals (or silence) from being excessively amplified. register address bit label default description r41 (29h) drc control 1 3:2 drc_mingain [1:0] 10 minimum gain the drc can use to attenuate audio signals 00 = 0db (default) 01 = -6db 10 = -12db 11 = -18db 1:0 drc_maxgain [1:0] 00 maximum gain the drc can use to boost audio signals 00 = 12db 01 = 18db (default) 10 = 24db 11 = 36db table 17 drc gain limits dynamic characteristics the dynamic behaviour determines how quickly t he drc responds to changing signal levels. note that the drc responds to the average (rms) signal amplitude over a period of time. drc_atk determines how quickly the drc gain decr eases when the signal amplitude is high. drc_dcy determines how quickly the drc gain incr eases when the signal amplitude is low. these register fields are described in table 18. no te that the register defaults are suitable for general purpose microphone use. register address bit label default description r41 (29h) drc control 1 15:12 drc_atk [3:0] 0011 gain attack rate (seconds/6db) 0000 = reserved 0001 = 182s 0010 = 363s 0011 = 726s (default) 0100 = 1.45ms 0101 = 2.9ms 0110 = 5.8ms 0111 = 11.6ms 1000 = 23.2ms 1001 = 46.4ms 1010 = 92.8ms 1011-1111 = reserved
WM8904 pre-production w pp, rev 3.3, september 2012 56 register address bit label default description 11:8 drc_dcy [3:0] 0010 gain decay rate (seconds/6db) 0000 = 186ms 0001 = 372ms 0010 = 743ms (default) 0011 = 1.49s 0100 = 2.97s 0101 = 5.94s 0110 = 11.89s 0111 = 23.78s 1000 = 47.56s 1001-1111 = reserved table 18 drc attack and decay rates note: for detailed information about drc attack and decay rates, please see wolfson application note wan0247. anti-clip control the drc includes an anti-clip feature to avoid si gnal clipping when the input amplitude rises very quickly. this feature uses a feed- forward technique for early detection of a rising signal level. signal clipping is avoided by dynamically increasing the gain attack rate when required. the anti-clip feature is enabled using the drc_anticlip bit. note that the feed-forward processing increases the latency in the input signal path. for low-latency applications (e.g. telephony), it may be desirable to reduce the delay, although this will also reduce the effectiveness of the anti-clip feature. t he latency is determined by the drc_ff_delay bit. if necessary, the latency can be minimised by disabling the anti-clip feature altogether. the drc anti-clip control bits are described in table 19. register address bit label default description r40 (28h) drc control 0 5 drc_ff_delay 1 feed-forward delay for anti-clip feature 0 = 5 samples 1 = 9 samples time delay can be calculated as 5/f s or 9/ f s , where f s is the sample rate. 1 drc_anticlip 1 anti-clip enable 0 = disabled 1 = enabled table 19 drc anti-clip control note that the anti-clip feature operates entirely in the digital domain. it cannot be used to prevent signal clipping in the analogue domain nor in t he source signal. anal ogue clipping can only be prevented by reducing the analogue signal gai n or by adjusting the source signal.
pre-production WM8904 w pp, rev 3.3, september 2012 57 quick release control the drc includes a quick-release feature to handle s hort transient peaks that are not related to the intended source signal. for example, in handhel d microphone recording, transient signal peaks sometimes occur due to user handling, key pre sses or accidental tapping against the microphone. the quick release feature ensures that these transients do not cause the intended signal to be masked by the longer time constants of drc_dcy. the quick-release feature is enabled by setting the drc_qr bit. when this bit is enabled, the drc measures the crest factor (peak to rms ratio) of t he input signal. a high crest fa ctor is indicative of a transient peak that may not be related to the int ended source signal. if the crest factor exceeds the level set by drc_qr_thr, then the normal decay rate (drc_dcy) is ignored and a faster decay rate (drc _qr_dcy) is used instead. the drc quick-release control bi ts are described in table 20. register address bit label default description r40 (28h) drc control 0 2 drc_qr 1 quick release enable 0 = disabled 1 = enabled r41 (29h) drc control 1 7:6 drc_qr_thr [1:0] 01 quick release crest factor threshold 00 = 12db 01 = 18db (default) 10 = 24db 11 = 30db 5:4 drc_qr_dcy [1:0] 00 quick release decay rate (seconds/6db) 00 = 0.725ms (default) 01 = 1.45ms 10 = 5.8ms 11 = reserved table 20 drc quick-release control gain smoothing the drc includes a gain smoothing filter in order to prevent gain ripples. a programmable level of hysteresis is also used to control the drc gain. this improves the handling of very low frequency input signals whose period is close to the drc a ttack/decay time. drc gain smoothing is enabled by default and it is recommended to us e the default register settings. the extent of the gain smoothing filter may be adjus ted or disabled using the control fields described in table 21. register address bit label default description r40 (28h) drc control 0 12:11 drc_gs_hyst _lvl [1:0] 00 gain smoothing hysteresis threshold 00 = low 01 = medium (recommended) 10 = high 11 = reserved 3 drc_gs_ena 1 gain smoothing enable 0 = disabled 1 = enabled 0 drc_gs_hyst 1 gain smoothing hysteresis enable 0 = disabled 1 = enabled table 21 drc gain smoothing
WM8904 pre-production w pp, rev 3.3, september 2012 58 initialisation when the drc is initialised, the gain is set to the level determined by the drc_startup_gain register field. the default setting is 0db, but values from -3db to + 6db are available, as described in table 22. register address bit label default description r40 (28h) drc control 0 10:6 drc_startup_ gain [4:0] 00110 initial gain at drc start-up 00000 = -3db 00001 = -2.5db 00010 = -2db 00011 = -1.5db 00100 = -1db 00101 = -0.5db 00110 = 0db (default) 00111 = 0.5db 01000 = 1db 01001 = 1.5db 01010 = 2db 01011 = 2.5db 01100 = 3db 01101 = 3.5db 01110 = 4db 01111 = 4.5db 10000 = 5db 10001 = 5.5db 10010 = 6db 10011 to 11111 = reserved table 22 drc initialisation
pre-production WM8904 w pp, rev 3.3, september 2012 59 retune tm mobile parametric equalizer (eq) the retune tm mobile parametric equaliser is a circ uit that can be enabled in the dac path. the function of the eq is to adjust the frequency characteristic of the output to compensate for unwanted frequency characteristics in the l oudspeaker (or other output transduce r). it can also be used to tailor the response according to user preferences, fo r example to accentuate or attenuate specific frequency bands to emulate different sound profiles or environments such as concert hall, rock etc. the eq is enabled using the eq_ena bit as shown in table 23. register address bit label default description r134 (86h) eq1 0 eq_ena 0 eq enable 0 = eq disabled 1 = eq enabled table 23 retune tm mobile parametric eq enable the eq can be configured to operate in two modes - ?default? mode or ?retune tm mobile? mode. default mode (5-band parametric eq) in default mode, the cut-off / centre frequencies are fixed as per table 24. the filter bandwidths are also fixed in default mode. the gain of the indi vidual bands (-12db to +12db ) can be controlled as described in table 25. note that the cut-off / centre frequencies noted in table 24 are applicable to a dac sample rate of 48khz. when using other sample rates, these fr equencies will be scaled in proportion to the selected sample rate. eq band cut-off/centre frequency 1 100 hz 2 300 hz 3 875 hz 4 2400 hz 5 6900 hz table 24 eq band cut-off / centre frequencies register address bit label default description r135 (87h) eq2 4:0 eq_b1_gain [4:0] 01100b (0db) eq band 1 gain (see table 26 for gain range) r136 (88h) eq3 4:0 eq_b2_gain [4:0] 01100b (0db) eq band 2 gain (see table 26 for gain range) r137 (89h) eq4 4:0 eq_b3_gain [4:0] 01100b (0db) eq band 3 gain (see table 26 for gain range) r138 (8ah) eq5 4:0 eq_b4_gain [4:0] 01100b (0db) eq band 4 gain (see table 26 for gain range) r139 (8bh) eq6 4:0 eq_b5_gain [4:0] 01100b (0db) eq band 5 gain (see table 26 for gain range) table 25 eq band gain control
WM8904 pre-production w pp, rev 3.3, september 2012 60 eq gain setting gain (db) 00000 -12 00001 -11 00010 -10 00011 -9 00100 -8 00101 -7 00110 -6 00111 -5 01000 -4 01001 -3 01010 -2 01011 -1 01100 0 01101 +1 01110 +2 01111 +3 10000 +4 10001 +5 10010 +6 10011 +7 10100 +8 10101 +9 10110 +10 10111 +11 11000 +12 11001 to 11111 reserved table 26 eq gain control retune tm mobile mode retune tm mobile mode provides a comprehensive facilit y for the user to define the cut-off/centre frequencies and filter bandwidth for each eq band, in addition to the gain controls already described. this enables the eq to be accurately customised fo r a specific transducer c haracteristic or desired sound profile. the eq enable and eq gain controls are the same as defined for the default mode. the additional coefficients used in retune tm mobile mode are held in registers r140 to r157. these coefficients are derived using tools provided in wolfson? s wisce? evaluation board control software. please contact your local wolfson representative for more details. eq filter characteristics the filter characteristics for each frequency band are shown in figure 30 to figure 34. these figures show the frequency response for a ll available gain settings, using default cut-off/centre frequencies and bandwidth.
pre-production WM8904 w pp, rev 3.3, september 2012 61 -15 -10 -5 0 5 10 15 1 10 100 1000 10000 100000 frequency (hz) gain (db) -15 -10 -5 0 5 10 15 1 10 100 1000 10000 100000 frequency (hz) gain (db) figure 30 eq band 1 ? low freq shelf filter response figure 31 eq band 2 ? peak filter response -15 -10 -5 0 5 10 15 1 10 100 1000 10000 100000 frequency (hz) gain (db) -15 -10 -5 0 5 10 15 1 10 100 1000 10000 100000 frequency (hz) gain (db) figure 32 eq band 3 ? peak filter response figure 33 eq band 4 ? peak filter response -15 -10 -5 0 5 10 15 1 10 100 1000 10000 100000 frequency (hz) gain (db) figure 34 eq band 5 ? high freq shelf filter response
WM8904 pre-production w pp, rev 3.3, september 2012 62 digital mixing the adc and dac data can be combined in various ways to support a range of different usage modes. data from either of the two adcs can be routed to either the left or the right channel of the digital audio interface. in addition, data from either of the digital audio interface channels can be routed to either the left or the right dac. see "digital audio interface" for more information on the audio interface. the WM8904 provides a dynamic range control ( drc) feature, which can apply compression and gain adjustment in the digital domain to either t he adc or dac signal path. this is effective in controlling signal levels under condi tions where input amplitude is unknown or varies over a wide range. the dacs can be configured as a mono mix of the two audio channel s. digital sidetone from the adcs can also be selectively mixed into the dac output path. digital mixing paths figure 35 shows the digital mixing paths available in the WM8904 digital core. figure 35 digital mixing paths
pre-production WM8904 w pp, rev 3.3, september 2012 63 the polarity of each adc output signal c an be changed under software control using the adcl_datinv and adcr_datinv register bits . the aifadcl_src and aifadcr_src register bits may be used to select which adc is used for the left and right digital audio interface data. these register bits are described in table 27. register address bit label default description r24 (18h) audio interface 0 7 aifadcl_src 0 left digital audio interface source 0 = left adc data is output on left channel 1 = right adc data is output on left channel 6 aifadcr_src 1 right digital audio interface source 0 = left adc data is output on right channel 1 = right adc data is output on right channel r38 (26h) adc digital 0 1 adcl_datinv 0 left adc invert 0 = left adc output not inverted 1 = left adc output inverted 0 adcr_datinv 0 right adc invert 0 = right adc output not inverted 1 = right adc output inverted table 27 adc routing and control the input data source for each dac can be changed under software control using register bits aifdacl_src and aifdacr_src. the polarity of each dac input may also be modified using register bits dacl_datinv and dacr_datinv. thes e register bits are described in table 28. register address bit label default description r24 (18h) audio interface 0 12 dacl_datinv 0 left dac invert 0 = left dac output not inverted 1 = left dac output inverted 11 dacr_datinv 0 right dac invert 0 = right dac output not inverted 1 = right dac output inverted 5 aifdacl_src 0 left dac data source select 0 = left dac outputs left interface data 1 = left dac outputs right interface data 4 aifdacr_src 1 right dac data source select 0 = right dac outputs left interface data 1 = right dac outputs right interface data table 28 dac routing and control
WM8904 pre-production w pp, rev 3.3, september 2012 64 dac interface volume boost a digital gain function is availabl e at the audio interface to boost the dac volume when a small signal is received on dacdat. this is c ontrolled using register bits dac_ boost [1:0]. to prevent clipping at the dac input, this function should not be used when the boosted dac data is expected to be greater than 0dbfs. the digital interface volume is controlled as shown in table 29. register address bit label default description r24 (18h) audio interface 0 10:9 dac_boost [1:0] 00 dac input volume boost 00 = 0db 01 = +6db (input data must not exceed -6dbfs) 10 = +12db (input data must not exceed -12dbfs) 11 = +18db (input data must not exceed -18dbfs) table 29 dac interface volume boost digital sidetone a digital sidetone is available w hen adcs and dacs are operating at the same sample rate. digital data from either left or right adc can be mixed wi th the audio interface data on the left and right dac channels. sidetone data is taken from the adc high pass filter output, to reduce low frequency noise in the sidetone (e.g. wind noise or mechanical vibration). when using the digital sidetone, it is recomm ended that the adcs are enabled before un-muting the dacs to prevent pop noise. the dac volumes and sidetone volumes should be set to an appropriate level to avoid clipping at the dac input. when digital sidetone is used, it is recommended that the charge pump operates in register control mode only (cp_dyn_pwr = 0). see ?charge pump? for details. the digital sidetone is contro lled as shown in table 30. register address bit label default description r32 (20h) dac digital 0 11:8 adcl_dac_svol [3:0] 0000 left digital sidetone volume (see table 31 for volume range) 7:4 adcr_dac_svol [3:0] 0000 right digital sidetone volume (see table 31 for volume range) 3:2 adc_to_dacl [1:0] 00 left dac digital sidetone source 00 = no sidetone 01 = left adc 10 = right adc 11 = reserved 1:0 adc_to_dacr [1:0] 00 right dac digital sidetone source 00 = no sidetone 01 = left adc 10 = right adc 11 = reserved table 30 digital sidetone control
pre-production WM8904 w pp, rev 3.3, september 2012 65 the digital sidetone volume settings are shown in table 31. adcl_dac_svol or adcr_dac_svol sidetone volume 0000 -36 0001 -33 0010 -30 0011 -27 0100 -24 0101 -21 0110 -18 0111 -15 1000 -12 1001 -9 1010 -6 1011 -3 1100 0 1101 0 1110 0 1111 0 table 31 digital sidetone volume
WM8904 pre-production w pp, rev 3.3, september 2012 66 digital-to-analogue converter (dac) the WM8904 dacs receive digital input data from the dacdat pin and via the digital sidetone path (see ?digital mixing? section). t he digital audio data is converted to oversampled bit streams in the on-chip, true 24-bit digital interpolation filters. the bitstream data enters two multi-bit, sigma-delta dacs, which convert them to high quality analogue audio signals. the wolfson smartdac? architecture offers reduced power consumption, whilst also delivering a reduction in high frequency noise and sensitivity to clock jitter. it also us es a dynamic element ma tching technique for high linearity and low distortion. the analogue outputs from the dacs are sent directly to the output pgas (see ?output signal path?). the dacs are enabled by the dacl_e na and dacr_ena register bits. register address bit label default description r18 (12h) power management 6 3 dacl_ena 0 left dac enable 0 = dac disabled 1 = dac enabled 2 dacr_ena 0 right dac enable 0 = dac disabled 1 = dac enabled table 32 dac enable control dac digital volume control the output level of each dac can be controlled di gitally over a range from -71.625db to 0db in 0.375db steps. the level of attenuation for an eight-bit code is detailed in table 34. the dac_vu bit controls the loading of digital volu me control data. when dac_vu is set to 0, the dacl_vol or dacr_vol control data is loaded into the respective control register, but does not actually change the digital gain setting. both left and right gain settings are updated when a 1 is written to dac_vu. this makes it possible to update the gain of both channels simultaneously. register address bit label default description r30 (1eh) dac digital volume left 8 dac_vu n/a dac volume update writing a 1 to this bit causes left and right dac volume to be updated simultaneously 7:0 dacl_vol [7:0] 1100_0000 (0db) left dac digital volume 00h = mute 01h = -71.625db 02h = -71.250db ? (0.375db steps) c0h to ffh = 0db (see table 34 for volume range) r31 (1fh) dac digital volume right 8 dac_vu n/a dac volume update writing a 1 to this bit causes left and right dac volume to be updated simultaneously 7:0 dacr_vol [7:0] 1100_0000 (0db) right dac digital volume 00h = mute 01h = -71.625db 02h = -71.250db ? (0.375db steps) c0h to ffh = 0db (see table 34 for volume range) table 33 dac digital volume control
pre-production WM8904 w pp, rev 3.3, september 2012 67 dacl_vol or dacr_vol volume (db) dacl_vol or dacr_vol volume (db) dacl_vol or dacr_vol volume (db) dacl_vol or dacr_vol volume (db) 0h mute 40h -48.000 80h -24.000 c0h 0.000 1h -71.625 41h -47.625 81h -23.625 c1h 0.000 2h -71.250 42h -47.250 82h -23.250 c2h 0.000 3h -70.875 43h -46.875 83h -22.875 c3h 0.000 4h -70.500 44h -46.500 84h -22.500 c4h 0.000 5h -70.125 45h -46.125 85h -22.125 c5h 0.000 6h -69.750 46h -45.750 86h -21.750 c6h 0.000 7h -69.375 47h -45.375 87h -21.375 c7h 0.000 8h -69.000 48h -45.000 88h -21.000 c8h 0.000 9h -68.625 49h -44.625 89h -20.625 c9h 0.000 ah -68.250 4ah -44.250 8ah -20.250 cah 0.000 bh -67.875 4bh -43.875 8bh -19.875 cbh 0.000 ch -67.500 4ch -43.500 8ch -19.500 cch 0.000 dh -67.125 4dh -43.125 8dh -19.125 cdh 0.000 eh -66.750 4eh -42.750 8eh -18.750 ceh 0.000 fh -66.375 4fh -42.375 8fh -18.375 cfh 0.000 10h -66.000 50h -42.000 90h -18.000 d0h 0.000 11h -65.625 51h -41.625 91h -17.625 d1h 0.000 12h -65.250 52h -41.250 92h -17.250 d2h 0.000 13h -64.875 53h -40.875 93h -16.875 d3h 0.000 14h -64.500 54h -40.500 94h -16.500 d4h 0.000 15h -64.125 55h -40.125 95h -16.125 d5h 0.000 16h -63.750 56h -39.750 96h -15.750 d6h 0.000 17h -63.375 57h -39.375 97h -15.375 d7h 0.000 18h -63.000 58h -39.000 98h -15.000 d8h 0.000 19h -62.625 59h -38.625 99h -14.625 d9h 0.000 1ah -62.250 5ah -38.250 9ah -14.250 dah 0.000 1bh -61.875 5bh -37.875 9bh -13.875 dbh 0.000 1ch -61.500 5ch -37.500 9ch -13.500 dch 0.000 1dh -61.125 5dh -37.125 9dh -13.125 ddh 0.000 1eh -60.750 5eh -36.750 9eh -12.750 deh 0.000 1fh -60.375 5fh -36.375 9fh -12.375 dfh 0.000 20h -60.000 60h -36.000 a0h -12.000 e0h 0.000 21h -59.625 61h -35.625 a1h -11.625 e1h 0.000 22h -59.250 62h -35.250 a2h -11.250 e2h 0.000 23h -58.875 63h -34.875 a3h -10.875 e3h 0.000 24h -58.500 64h -34.500 a4h -10.500 e4h 0.000 25h -58.125 65h -34.125 a5h -10.125 e5h 0.000 26h -57.750 66h -33.750 a6h -9.750 e6h 0.000 27h -57.375 67h -33.375 a7h -9.375 e7h 0.000 28h -57.000 68h -33.000 a8h -9.000 e8h 0.000 29h -56.625 69h -32.625 a9h -8.625 e9h 0.000 2ah -56.250 6ah -32.250 aah -8.250 eah 0.000 2bh -55.875 6bh -31.875 abh -7.875 ebh 0.000 2ch -55.500 6ch -31.500 ach -7.500 ech 0.000 2dh -55.125 6dh -31.125 adh -7.125 edh 0.000 2eh -54.750 6eh -30.750 aeh -6.750 eeh 0.000 2fh -54.375 6fh -30.375 afh -6.375 efh 0.000 30h -54.000 70h -30.000 b0h -6.000 f0h 0.000 31h -53.625 71h -29.625 b1h -5.625 f1h 0.000 32h -53.250 72h -29.250 b2h -5.250 f2h 0.000 33h -52.875 73h -28.875 b3h -4.875 f3h 0.000 34h -52.500 74h -28.500 b4h -4.500 f4h 0.000 35h -52.125 75h -28.125 b5h -4.125 f5h 0.000 36h -51.750 76h -27.750 b6h -3.750 f6h 0.000 37h -51.375 77h -27.375 b7h -3.375 f7h 0.000 38h -51.000 78h -27.000 b8h -3.000 f8h 0.000 39h -50.625 79h -26.625 b9h -2.625 f9h 0.000 3ah -50.250 7ah -26.250 bah -2.250 fah 0.000 3bh -49.875 7bh -25.875 bbh -1.875 fbh 0.000 3ch -49.500 7ch -25.500 bch -1.500 fch 0.000 3dh -49.125 7dh -25.125 bdh -1.125 fdh 0.000 3eh -48.750 7eh -24.750 beh -0.750 feh 0.000 3fh -48.375 7fh -24.375 bfh -0.375 ffh 0.000 table 34 dac digital volume range
WM8904 pre-production w pp, rev 3.3, september 2012 68 dac soft mute and soft un-mute the WM8904 has a soft mute function. when enabled, this gradually attenuates the volume of the dac output. when soft mute is disabled, the gain will either gradually ramp back up to the digital gain setting, or return instantly to the digital gai n setting, depending on the dac_unmute_ramp register bit. to mute the dac, this function must be enabled by setting dac_mute to 1. soft mute mode would typically be enabled (dac _unmute_ramp = 1) when using dac_mute during playback of audio data so that when dac_mu te is subsequently disabled, the sudden volume increase will not create pop noise by jumping immediat ely to the previous volume level (e.g. resuming playback after pausing during a track). soft mute mode would typically be disabled (dac_ unmute_ramp = 0) when un-muting at the start of a music file, in order that the first part of t he track is not attenuated (e.g. when starting playback of a new track, or resuming playback after pausing between tracks). dac muting and un-muting using volume control bits dacl_vol and dacr_vol. dac muting and un-muting using the dac_mute bit. if soft mute mode is not enabled (dac_unmute_ramp = 0): setting the dac_mute bit causes the volume to ramp down at a rate controlled by dac_muterate. clearing the dac_mute bit causes the volume to return to the un-muted level immediately. dac muting and un-muting using the dac_mute bit. if soft mute mode is enabled (dac_unmute_ramp = 1): setting the dac_mute bit causes the volume to ramp down. clearing the dac_mute bit causes the volume to ramp up to the un-muted level at a rate controlled by dac_muterate. figure 36 dac mute control the volume ramp rate during soft mute and un-mute is controlled by the dac_muterate bit. ramp rates of fs/32 and fs/2 can be selected, as shown in table 35. the ramp rate determines the rate at which the volume is increased or decreased. the actual ramp time depends on the extent of the difference between the muted and un-muted volume settings.
pre-production WM8904 w pp, rev 3.3, september 2012 69 register address bit label default description r33 (21h) dac digital 1 10 dac_mutera te 0 dac soft mute ramp rate 0 = fast ramp (fs/2, maximum ramp time is 10.7ms at fs=48k) 1 = slow ramp (fs/32, maximum ramp time is 171ms at fs=48k) 9 dac_unmute _ramp 0 dac soft mute mode 0 = disabling soft-mute (dac_mute=0) will cause the dac volume to change immediately to dacl_vol and dacr_vol settings 1 = disabling soft-mute (dac_mute=0) will cause the dac volume to ramp up gradually to the dacl_vol and dacr_vol settings 3 dac_mute 1 dac soft mute control 0 = dac un-mute 1 = dac mute table 35 dac soft-mute control dac mono mix a dac digital mono-mix mode can be enabled using t he dac_mono register bit. this mono mix will be output on whichever dac is enabled. to prevent clipping, a -6db attenuation is automatically applied to the mono mix. the mono mix is only supported when one or other da c is disabled. when the mono mix is selected, then the mono mix is output on the enabled dac only; there is no output from the disabled dac. if dacl_ena and dacr_ena are both set, then stereo operation applies. register address bit label default description r33 (21h) dac digital 1 12 dac_mono 0 dac mono mix 0 = stereo 1 = mono (mono mix output on enabled dac) table 36 dac mono mix dac de-emphasis digital de-emphasis can be applied to the dac pl ayback data (e.g. when the data comes from a cd with pre-emphasis used in the recording). de-emphas is filtering is available for sample rates of 48khz, 44.1khz and 32khz. see ?digit al filter characteristics? fo r details of de-emphasis filter characteristics. register address bit label default description r33 (21h) dac digital 1 2:1 deemph [1:0] 00 dac de-emphasis control 00 = no de-emphasis 01 = 32khz sample rate 10 = 44.1khz sample rate 11 = 48khz sample rate table 37 dac de-emphasis control
WM8904 pre-production w pp, rev 3.3, september 2012 70 dac sloping stopband filter two dac filter types are available, selected by the register bit dac_sb_filt. when operating at sample rates <= 24khz (eg. during voice comm unication) it is recommended that the sloping stopband filter type is selected (dac_sb_filt=1) to reduce out-of-band noise which can be audible at low dac sample rates. see ?digital filter characte ristics? for details of dac filter characteristics. register address bit label default description r33 (21h) dac digital 1 11 dac_sb_filt 0 selects dac filter characteristics 0 = normal mode 1 = sloping stopband mode (recommended when fs ??? 24khz ? table 38 dac sloping stopband filter dac oversampling ratio (osr) the dac oversampling rate is programmable to allow power consumption versus audio performance trade-offs. the default oversampling rate is low for reduced power consumpt ion; using the higher osr setting improves the dac signal-to-noise performance. register address bit label default description r33 (21h) dac digital 1 6 dac_osr128 0 dac oversample rate select 0 = low power (normal osr) 1 = high performance (double osr) table 39 dac oversampling control
pre-production WM8904 w pp, rev 3.3, september 2012 71 output signal path the outputs hpoutl and lineoutl are normally derived from the left dac output, whilst the outputs hpoutr and lineoutr are normally derived from the right dac output, as illustrated in figure 37. a multiplexer is provided on each output path to select the bypassl or bypassr analogue input signals in place of the dac outputs. a feedback path for common mode noise rejection is provided at hpoutfb and lineoutfb for the headphone and line outputs respectively. this pi n must be connected to ground for normal operation. each analogue output can be separately enabled; independent volume control is also provided for each output. the output signal paths and associated cont rol registers are illustrated in figure 37. see ?analogue outputs? for details of the ex ternal connections to these outputs. hpoutl hpoutfb charge pump cpvdd cpgnd cpvoutp cpcb cpca cpvoutn hpoutr dc servo avdd dcvdd hpout and lineout drivers bypassl bypassr hpoutl_mute hpout_vu hpoutlzc hpoutl_vol (-57db to +6db, 1 db steps) hpoutr_mute hpout_vu hpoutrzc hpoutr_vol (-57db to +6db, 1 db steps) lineoutl_mute lineout_vu lineoutlzc lineoutl_vol (-57db to +6db, 1 db steps) lineoutr_mute lineout_vu lineoutrzc lineoutr_vol (-57db to +6db, 1 db steps) hpl_pga_ena hpr_pga_ena lineoutl_pga_ena lineoutr_pga_ena lineoutl lineoutfb lineoutr dac l dac r m u x m u x m u x m u x bypassl bypassr dacl dacr hpl_byp_ena hpr_byp_ena lineoutl_byp_ena lineoutr_byp_ena figure 37 output signal path and control registers
WM8904 pre-production w pp, rev 3.3, september 2012 72 output signal paths enable the output pgas for each analogue output pin can be enabled and disabled using the register bits described in table 40. note that the headphone outputs and line outputs are also controlled by fields located within register r90 and r94, which provide suppre ssion of pops & clicks when enabling and disabling these signal paths. these registers are descri bed in the following ?headphone / line output signal paths enable? section. under recommended usage conditions, all the cont rol bits associated with enabling the headphone outputs and the line outputs will be configured by scheduling the default start-up and shutdown sequences as described in the ?control write sequence r? section. in these cases, the user does not need to set the register fields in r14, r15, r90 and r94 directly. register address bit label default description r14 (0eh) power management 2 1 hpl_pga_ena 0 left headphone output enable 0 = disabled 1 = enabled 0 hpr_pga_ena 0 right headphone output enable 0 = disabled 1 = enabled r15 (0fh) power management 3 1 lineoutl_pga_ ena 0 left line output enable 0 = disabled 1 = enabled 0 lineoutr_pga _ena 0 right line output enable 0 = disabled 1 = enabled table 40 output signal paths enable to enable the output pgas and multiplexers, the re ference voltage vmid and the bias current must also be enabled. see ?reference voltages and master bias? for details of the associated controls vmid_res and bias_ena. headphone / line output signal paths enable the output paths can be actively discharged to agnd through internal resistors if desired. this is desirable at start-up in order to achieve a know n output stage condition prior to enabling the vmid reference voltage. this is also desirable in shut down to prevent the exter nal connections from being affected by the internal circuits. the ground-referenced headphone outputs and line outputs are shorted to agnd by default; the short circuit is removed on each of these paths by setting the applicable fields hpl_rmv_short, hpr_rm v_short, lineoutl_rmv_short or lineoutr_rmv_short. the ground-referenced headphone output and line output drivers are designed to suppress pops and clicks when enabled or disabled. however, it is necessary to control the drivers in accordance with a defined sequence in start-up and shutdown to achieve the pop suppression. it is also necessary to schedule the dc servo offset correct ion at the appropriate point in the sequence (see ?dc servo?). table 41 and table 42 descr ibe the recommended sequences for enabling and disabling these output drivers.
pre-production WM8904 w pp, rev 3.3, september 2012 73 sequence headphone enable lineout enable step 1 hpl_ena = 1 hpr_ena = 1 lineoutl_ena = 1 lineoutr_ena = 1 step 2 hpl_ena_dly = 1 hpr_ena_dly = 1 lineoutl_ena_dly = 1 lineoutr_ena_dly = 1 step 3 dc offset correction dc offset correction step 4 hpl_ena_outp = 1 hpr_ena_outp = 1 lineoutl_ena_outp = 1 lineoutr_ena_outp = 1 step 5 hpl_rmv_short = 1 hpr_rmv_short = 1 lineoutl_rmv_short = 1 lineoutr_rmv_short = 1 table 41 headphone / line output enable sequence sequence headphone disable lineout disable step 1 hpl_rmv_short = 0 hpr_rmv_short = 0 lineoutl_rmv_short = 0 lineoutr_rmv_short = 0 step 2 hpl_ena = 0 hpl_ena_dly = 0 hpl_ena_outp = 0 hpr_ena = 0 hpr_ena_dly = 0 hpr_ena_outp = 0 lineoutl_ena = 0 lineoutl_ena_dly = 0 lineoutl_ena_outp = 0 lineoutr_ena = 0 lineoutr_ena_dly = 0 lineoutr_ena_outp = 0 table 42 headphone / line output disable sequence the registers relating to headphone / line output pop suppression control are defined in table 43. register address bit label default description r90 (5ah) analogue hp 0 7 hpl_rmv_shor t 0 removes hpl short 0 = hpl short enabled 1 = hpl short removed for normal operation, this bit should be set as the final step of the hpl enable sequence. 6 hpl_ena_outp 0 enables hpl output stage 0 = disabled 1 = enabled for normal operation, this bit should be set to 1 after the dc offset cancellation has been scheduled. 5 hpl_ena_dly 0 enables hpl intermediate stage 0 = disabled 1 = enabled for normal operation, this bit should be set to 1 after the output signal path has been configured, and before dc offset cancellation is scheduled. this bit should be set with at least 20us delay after hpl_ena.
WM8904 pre-production w pp, rev 3.3, september 2012 74 register address bit label default description 4 hpl_ena 0 enables hpl input stage 0 = disabled 1 = enabled for normal operation, this bit should be set as the first step of the hpl enable sequence. 3 hpr_rmv_sho rt 0 removes hpr short 0 = hpr short enabled 1 = hpr short removed for normal operation, this bit should be set as the final step of the hpr enable sequence. 2 hpr_ena_outp 0 enables hpr output stage 0 = disabled 1 = enabled for normal operation, this bit should be set to 1 after the dc offset cancellation has been scheduled. 1 hpr_ena_dly 0 enables hpr intermediate stage 0 = disabled 1 = enabled for normal operation, this bit should be set to 1 after the output signal path has been configured, and before dc offset cancellation is scheduled. this bit should be set with at least 20us delay after hpr_ena. 0 hpr_ena 0 enables hpr input stage 0 = disabled 1 = enabled for normal operation, this bit should be set as the first step of the hpr enable sequence.
pre-production WM8904 w pp, rev 3.3, september 2012 75 register address bit label default description r94 (5eh) analogue lineout 0 7 lineoutl_rmv_ short 0 removes lineoutl short 0 = lineoutl short enabled 1 = lineoutl short removed for normal operation, this bit should be set as the final step of the lineoutl enable sequence. 6 lineoutl_ena_ outp 0 enables lineoutl output stage 0 = disabled 1 = enabled for normal operation, this bit should be set to 1 after the dc offset cancellation has been scheduled. 5 lineoutl_ena_ dly 0 enables lineoutl intermediate stage 0 = disabled 1 = enabled for normal operation, this bit should be set to 1 after the output signal path has been configured, and before dc offset cancellation is scheduled. this bit should be set with at least 20us delay after lineoutl_ena. 4 lineoutl_ena 0 enables lineoutl input stage 0 = disabled 1 = enabled for normal operation, this bit should be set as the first step of the lineoutl enable sequence. 3 lineoutr_rmv _short 0 removes lineoutr short 0 = lineoutr short enabled 1 = lineoutr short removed for normal operation, this bit should be set as the final step of the lineoutr enable sequence. 2 lineoutr_ena_ outp 0 enables lineoutr output stage 0 = disabled 1 = enabled for normal operation, this bit should be set to 1 after the dc offset cancellation has been scheduled. 1 lineoutr_ena_ dly 0 enables lineoutr intermediate stage 0 = disabled 1 = enabled for normal operation, this bit should be set to 1 after the output signal path has been configured, and before dc offset cancellation is scheduled. this bit should be set with at least 20us delay after lineoutr_ena. 0 lineoutr_ena 0 enables lineoutr input stage 0 = disabled 1 = enabled for normal operation, this bit should be set as the first step of the lineoutr enable sequence. table 43 headphone / line output pop suppression control
WM8904 pre-production w pp, rev 3.3, september 2012 76 output mux control by default, the dac outputs are routed directly to t he respective output pgas. a multiplexer (mux) is provided on each output path to select the bypassl or bypassr analogue signals from the left/right input pgas in place of the dac outputs. the output multiplexers are configured using the register bits described in table 44. register address bit label default description r61 (3dh) analogue out12 zc 3 hpl_byp_ena 0 selects input for left headphone output mux 0 = left dac 1 = left input pga (analogue bypass) 2 hpr_byp_ena 0 selects input for right headphone output mux 0 = right dac 1 = right input pga (analogue bypass) 1 lineoutl_byp_ ena 0 selects input for left line output mux 0 = left dac 1 = left input pga (analogue bypass) 0 lineoutr_byp_ ena 0 selects input for right line output mux 0 = right dac 1 = right input pga (analogue bypass) table 44 output mux control output volume control each analogue output can be independently controll ed. the headphone output control fields are described in table 45. the line output control fields are described in table 46. the output pins are described in more detail in ?analogue outputs?. the volume and mute status of each output can be cont rolled individually using t he bit fields shown in table 45 and table 46. to prevent ?zipper noise? when a volume adjustment is made, a zero-cross function is provided on all output paths. when this function is enabled, volume updates will not take place until a zero-crossing is detected. in the event of a long period without zero-crossings, a timeout will apply. the timeout must be enabled by setting the toclk_ena bit, as defined in ?clocking and sample rates?. the volume update bits control the loading of the output driver volume data. for example, when hpout_vu is set to 0, the headphone volume dat a can be loaded into the respective control register, but will not actually change the gain setting. the left and right headphone volume settings are updated when a 1 is written to hpout_vu. this makes it possible to update the gain of a left/right pair of output paths simultaneously.
pre-production WM8904 w pp, rev 3.3, september 2012 77 register address bit label default description r57 (39h) analogue out1 left 8 hpoutl_mute 0 left headphone output mute 0 = un-mute 1 = mute 7 hpout_vu 0 headphone output volume update writing a 1 to this bit will update hpoutl and hpoutr volumes simultaneously. 6 hpoutlzc 0 left headphone output zero cross enable 0 = disabled 1 = enabled 5:0 hpoutl_vol [5:0] 10_1101 left headphone output volume 000000 = -57db 000001 = -56db (? 1db steps) 111001 = 0db (? 1db steps) 111110 = +5db 111111 = +6db r58 (3ah) analogue out1 right 8 hpoutr_mute 0 right headphone output mute 0 = un-mute 1 = mute 7 hpout_vu 0 headphone output volume update writing a 1 to this bit will update hpoutl and hpoutr volumes simultaneously. 6 hpoutrzc 0 right headphone output zero cross enable 0 = disabled 1 = enabled 5:0 hpoutr_vol [5:0] 10_1101 right headphone output volume 000000 = -57db 000001 = -56db (? 1db steps) 111001 = 0db (? 1db steps) 111110 = +5db 111111 = +6db table 45 volume control for hpoutl and hpoutr
WM8904 pre-production w pp, rev 3.3, september 2012 78 register address bit label default description r59 (3bh) analogue out2 left 8 lineoutl_mute 0 left line output mute 0 = un-mute 1 = mute 7 lineout_vu 0 line output volume update writing a 1 to this bit will update lineoutl and lineoutr volumes simultaneously. 6 lineoutlzc 0 left line output zero cross enable 0 = disabled 1 = enabled 5:0 lineoutl_vol [5:0] 11_1001 left line output volume 000000 = -57db 000001 = -56db (? 1db steps) 111001 = 0db (? 1db steps) 111110 = +5db 111111 = +6db r60 (3ch) analogue out2 right 8 lineoutr_mut e 0 right line output mute 0 = un-mute 1 = mute 7 lineout_vu 0 line output volume update writing a 1 to this bit will update lineoutl and lineoutr volumes simultaneously. 6 lineoutrzc 0 right line output zero cross enable 0 = disabled 1 = enabled 5:0 lineoutr_vol [5:0] 11_1001 right line output volume 000000 = -57db 000001 = -56db (? 1db steps) 111001 = 0db (? 1db steps) 111110 = +5db 111111 = +6db table 46 volume control for lineoutl and lineoutr
pre-production WM8904 w pp, rev 3.3, september 2012 79 analogue outputs the WM8904 has four analogue output pins: ? headphone outputs, hpoutl and hpoutr, with feedback hpoutfb ? line outputs, lineoutl and lineoutr, with feedback lineoutfb the output signal paths and associated contro l registers are illustrated in figure 37. headphone outputs ? hpoutl and hpoutr the headphone outputs are designed to drive 16 ? or 32 ? headphones. these outputs are ground- referenced, i.e. no series capacitor is requi red between the pins and the headphone load. they are powered by an on-chip charge pump (see ?charge pump? section). signal volume at the headphone outputs is controlled as shown in table 45. the ground-referenced outputs incorporates a co mmon mode, or ground loop, feedback path which provides rejection of system-related ground noise . the return path for the hpoutl and hpoutr outputs is via hpoutfb. this pin must be c onnected to ground for normal operation of the headphone output. no register configuration is required. line outputs ? lineoutl and lineoutr the line outputs are identical to the headphone output s in design. they are ground-referenced and powered by the on-chip charge pump. signal volume at the line outputs is controlled as shown in table 46. note that these outputs are intended for driving line loads, as the charge pump powering both the headphone and line outputs can only provide sufficient power to drive one set of headphones at any given time. the ground-referenced outputs incorporates a co mmon mode, or ground loop, feedback path which provides rejection of system-related ground noise. the return path for the lineoutl and lineoutr outputs is via lineoutfb. this pin must be c onnected to ground for normal operation of the line output. no register configuration is required.
WM8904 pre-production w pp, rev 3.3, september 2012 80 external components for ground referenced outputs it is recommended to connect a zobel network to the ground-referenced outputs hpoutl, hpoutr, lineoutl and lineoutr in order to ensure best audio performance in all applications. the components of the zobel network have the effe ct of dampening high frequency oscillations or instabilities that can arise outside the audio band under certain conditions. possi ble sources of these instabilities include the inductive load of a headphone coil or an active load in the form of an external line amplifier. the capacitance of l engthy cables or pcb tracks can also lead to amplifier instability. the zobel network should comprise a 20 ? resistor and 100nf capacitor in series with each other, as illustrated in figure 38. note that the zobel network is recommended for best audio quality and amplifier stability in all cases. figure 38 zobel network components for hp outl, hpoutr, lineoutl and lineoutr
pre-production WM8904 w pp, rev 3.3, september 2012 81 reference voltages and master bias this section describes the analogue reference voltage and bias current controls. note that, under the recommended usage conditions of the WM8904, these features will be configured by scheduling the default start-up and shutdown sequences as described in the ?control write sequencer? section. in these cases, the user does not need to set these register fields directly. analogue reference and master bias the analogue circuits in the WM8904 require a mi d-rail analogue reference voltage, vmid. this reference is generated from avdd via a programmable resistor chain. vmid is enabled by setting the vmid_ena regist er bit. the programmable resistor chain is configured by vmid_res [1:0], and can be used to opt imise the reference for normal operation, low power standby or for fast start-up as described in table 47. for normal operation, the vmid_res field should be set to 01. the vmid_buf_ena bit allows the buffer ed vmid reference to be connected to unused inputs/outputs. the analogue circuits in the WM8904 require a bias current. the bi as current is enabled by setting bias_ena. note that the bias current source requires vmid to be enabled also. the bias current is controlled using the isel register field. note that the isel register should only be changed as part of the ?low power mode enable? sequence described in table 48. in all other cases, it is recommended that the isel register is not changed from the default setting. register address bit label default description r5 (05h) vmid control (0) 6 vmid_buf_ ena 0 enable vmid buffer to unused inputs/outputs 0 = disabled 1 = enabled 2:1 vmid_res [1:0] 00 vmid divider enable and select 00 = vmid disabled (for off mode) 01 = 2 x 50k divider (for normal operation) 10 = 2 x 250k divider (for low power standby) 11 = 2 x 5k divider (for fast start-up) 0 vmid_ena 0 enable vmid master bias current source 0 = disabled 1 = enabled r4 (04h) bias control (0) 3:2 isel [1:0] 10 master bias control 00 = low power bias 01 = reserved 10 = high performance bias (default) 11 = reserved note that the isel register should only be changed as part of the low power mode enable/disable sequences. 0 bias_ena 0 enables the normal bias current generator (for all analogue functions) 0 = disabled 1 = enabled table 47 reference voltages and master bias enable
WM8904 pre-production w pp, rev 3.3, september 2012 82 low power playback mode the analogue circuits of the WM8904 r equire a bias current. the default bias configuration is suitable for typical applications, and does not require any user adjustment. for lowest power consumption in headphone or line output playback mode, the WM8904 bias settings must be configured using the regist er sequence described in table 48. note that the low power playback bias settings are recommended for dac / playback modes only; they are not suitable for adc / record path modes. register address value 04h 0011h 08h 0019h cch 0030h 5bh 0002h 63h 2425h 64h 2b23h a1h 0002h 65h 00c0h a1h 0000h table 48 low power playback mode enable sequence the low power mode disable sequenc e is described in table 49. note that the low power playback bias settings are not suitable for adc / record path modes; the low power configuration must be disabled for these modes. register address value 04h 0019h 08h 0001h cch 0000h 5bh 0000h 63h 1f25h 64h 2b19h a1h 0002h 65h 01c0h a1h 0000h table 49 low power playback mode disable sequence
pre-production WM8904 w pp, rev 3.3, september 2012 83 pop suppression control the WM8904 incorporates wolfson?s silentsw itch? technology which enables pops normally associated with start-up, shutdown or signal path control to be suppressed. to achieve maximum benefit from these features, careful attention is required to the sequence and ti ming of these controls. note that, under the recommended usage conditions of the WM8904, these features will be configured by running the default start-up and s hutdown sequences as described in the ?control write sequencer? section. in these cases, the user does not need to set these register fields directly. the pop suppression controls relating to the h eadphone / line output drivers are described in the ?output signal path? section. disabled input control the analogue inputs to the WM8904 are biased to vmid in normal operation. in order to avoid audible pops caused by a disabl ed signal path dropping to agnd, the WM8904 can maintain these connections at vmid when the relevant input stage is disabled. this is achieved by connecting a buffered vmid reference to the input. the buffered vmid reference is enabled by setting vmid_buf_ena; when the buffered vmid reference is enabled, it is connected to any unused input pins. register address bit label default description r5 (05h) vmid control 0 6 vmid_buf_ena 0 vmid buffer to unused inputs/outputs 0 = disabled 1 = enabled 0 vmid_ena 0 vmid buffer enable 0 = disabled 1 = enabled table 50 disabled line input control
WM8904 pre-production w pp, rev 3.3, september 2012 84 charge pump the WM8904 incorporates a dual-mode charge pump which generates the supply rails for the headphone and line output drivers, hpoutl, hpoutr, and lineoutl and lineoutr. the charge pump has a single supply input, cpvdd, and generates split rails cpvoutp and cpvoutn according to the selected mode of operation. the charge pump connections are illustrated in figure 39 (see the ?electrical characteristics? section fo r external component values). an input decoupling capacitor may also be required at cpv dd, depending upon the system configuration. figure 39 charge pump external connections the charge pump is enabled by setting the cp_ena bit. when enabled, the c harge pump adjusts the output voltages (cpvoutp and cpvoutn) as well as the switching frequency in order to optimise the power consumption according to the operating conditions. this can take two forms, which are selected using the cp_dyn_pwr register bit. ? register control (cp_dyn_pwr = 0) ? dynamic control (cp_dyn_pwr = 1) under register control, the hpoutl_vol, hpoutr_vol, lineoutl_vol and lineoutr_vol register settings are used to contro l the charge pump mode of operation. under dynamic control, the audio signal level in t he dac is used to control the charge pump mode of operation. this is the wolfson ?class w? mode, wh ich allows the power consumption to be optimised in real time, but can only be used if the dac is the only signal source. this mode should not be used if any of the bypass paths are used to feed analogue inputs into the output signal path. under the recommended usage conditions of the WM8904, the charge pump will be enabled by running the default headphone start-up sequence as described in the ?control write sequencer? section. (similarly, it will be disabled by running the shutdown sequence.) in these cases, the user does not need to write to the cp_ena bit. the c harge pump operating mode defaults to register control; dynamic control may be selected by setti ng the cp_dyn_pwr register bit, if appropriate. when digital sidetone is used (see ?digital mixing?), it is recommended that the charge pump operates in register control mode only (cp_dyn_ pwr = 0). this is because the dynamic control mode (class w) does not measure the sidetone signal level and hence the charge pump configuration cannot be optimised fo r all signal conditions when digita l sidetone is enabled; this could lead to signal clipping. note that the charge pump clock is derived from internal clock sysclk; this may be derived from mclk directly or else using the fll output, as determined by the sysclk_src bit. under normal circumstances an external clock signal must be pr esent for the charge pump to function. however, the fll has a free-running mode that does not require an external clock but will generate an internal clock suitable for running the charge pump. the cl ock division from sysclk is handled transparently by the WM8904 without user intervention, as long as sysclk and sample rates are set correctly. refer to the ?clocking and sample rates? section for more detail on the fll and clocking configuration.
pre-production WM8904 w pp, rev 3.3, september 2012 85 the charge pump control fields are described in table 51. register address bit label default description r98 (62h) charge pump 0 0 cp_ena 0 enable charge-pump digits 0 = disable 1 = enable r104 (68h) class w (0) 0 cp_dyn_pwr 0 enable dynamic charge pump power control 0 = charge pump controlled by volume register settings (class g) 1 = charge pump controlled by real- time audio level (class w) class w is recommended for lowest power consumption table 51 charge pump control dc servo the WM8904 provides four dc servo circuits, two on the headphone outputs hpoutl and hpoutr and two on the line outputs lineoutl and lineoutr, to remove dc offset from these ground- referenced outputs. when enabled, the dc servos ensur e that the dc level of these outputs remains within 1mv of ground. removal of the dc offset is important because any deviation from gnd at the output pin will cause current to flow through t he load under quiescent c onditions, resulting in increased power consumption. additionally, the pres ence of dc offsets can result in audible pops and clicks at power up and power down. the recommended usage of the dc servo is initialis ed by running the default start-up sequence as described in the ?control write sequencer? section. the default start-up sequenc e executes a series of dc offset corrections, after which the meas ured offset correction is maintained on the headphone output channels. if a different usage is required, e.g. if a periodic dc offset correction is required, then the default start-up sequence may be modified acco rding to specific requirements. the relevant control fields are described in the follo wing paragraphs and are defined in table 52. dc servo enable and start-up the dc servo circuits are enabled on hpoutl and hpoutr by setting dcs_ena_chan_0 and dcs_ena_chan_1 respectively. similarly, t he dc servo circuits ar e enabled on lineoutl and lineoutr by setting dcs_ena_chan_2 and dcs _ena_chan_3 respectively when the dc servo is enabled, the dc offset correction c an be commanded in a number of different ways, including single-shot and peri odically recurring events. writing a logic 1 to dcs_trig_startup_ n initiates a series of dc offset measurements and applies the necessary correction to the associat ed output; (?n? = 3 for lineoutr channel, 2 for lineoutl channel, 1 for hpoutr channel, 0 for hp outl channel). on completion, the output will be within 1mv of agnd. this is the dc servo mode selected by the default start-up sequence. completion of the dc offset correction tri ggered in this way is indicated by the dcs_startup_complete field, as described in table 52. typically, this operation takes 86ms per channel. writing a logic 1 to dcs_trig_dac_wr_ n causes the dc offset correction to be set to the value contained in the dcs_dac_wr_val_ n fields in registers r73 to r 76. this mode is useful if the required offset correction has already been det ermined and stored; it is faster than the dcs_trig_startup_ n mode, but relies on the accuracy of the stored settings. completion of the dc offset correction triggered in this way is i ndicated by the dcs_dac_wr_complete field, as described in table 52. typically, this operation takes 2ms per channel. when using either of the dc servo options above, the status of the dc offset correction process is indicated by the dcs_cal_complete fiel d; this is the logical or of the dcs_startup_complete and dcs_d ac_wr_complete fields.
WM8904 pre-production w pp, rev 3.3, september 2012 86 the dc servo control fields associated with st art-up operation are described in table 52. it is important to note that, to minimise audible pops /clicks, the start-up and dac write modes of dc servo operation should be commanded as part of a control sequence which includes muting and shorting of the headphone outputs; a suitable sequence is defined in the default start-up sequence. register address bit label default description r68 (44h) dc servo 1 7 dcs_trig_star tup_3 0 writing 1 to this bit selects start-up dc servo mode for lineoutr. in readback, a value of 1 indicates that the dc servo start-up correction is in progress. 6 dcs_trig_star tup_2 0 writing 1 to this bit selects start-up dc servo mode for lineoutl. in readback, a value of 1 indicates that the dc servo start-up correction is in progress. 5 dcs_trig_star tup_1 0 writing 1 to this bit selects start-up dc servo mode for hpoutr. in readback, a value of 1 indicates that the dc servo start-up correction is in progress. 4 dcs_trig_star tup_0 0 writing 1 to this bit selects start-up dc servo mode for hpoutl. in readback, a value of 1 indicates that the dc servo start-up correction is in progress. 3 dcs_trig_dac_ wr_3 0 writing 1 to this bit selects dac write dc servo mode for lineoutr. in readback, a value of 1 indicates that the dc servo dac write correction is in progress. 2 dcs_trig_dac_ wr_2 0 writing 1 to this bit selects dac write dc servo mode for lineoutl. in readback, a value of 1 indicates that the dc servo dac write correction is in progress. 1 dcs_trig_dac_ wr_1 0 writing 1 to this bit selects dac write dc servo mode for hpoutr. in readback, a value of 1 indicates that the dc servo dac write correction is in progress. 0 dcs_trig_dac_ wr_0 0 writing 1 to this bit selects dac write dc servo mode for hpoutl. in readback, a value of 1 indicates that the dc servo dac write correction is in progress. r67 (43h) dc servo 0 3 dcs_ena_chan _3 0 dc servo enable for lineoutr 0 = disabled 1 = enabled 2 dcs_ena_chan _2 0 dc servo enable for lineoutl 0 = disabled 1 = enabled 1 dcs_ena_chan _1 0 dc servo enable for hpoutr 0 = disabled 1 = enabled 0 dcs_ena_chan _0 0 dc servo enable for hpoutl 0 = disabled 1 = enabled
pre-production WM8904 w pp, rev 3.3, september 2012 87 register address bit label default description r73 (49h) dc servo 6 7:0 dcs_dac_wr_v al_3 [7:0] 0000 0000 dc offset value for lineoutr in dac write dc servo mode in two's complement format. in readback, the current dc offset value is returned in two's complement format. two?s complement format: lsb is 0.25mv. range is +/-32mv r74 (4ah) dc servo 7 7:0 dcs_dac_wr_v al_2 [7:0] 0000 0000 dc offset value for lineoutl in dac write dc servo mode in two's complement format. in readback, the current dc offset value is returned in two's complement format. two?s complement format: lsb is 0.25mv. range is +/-32mv r75 (4bh) dc servo 8 7:0 dcs_dac_wr_v al1 [7:0] 0000 0000 dc offset value for hpoutr in dac write dc servo mode in two's complement format. in readback, the current dc offset value is returned in two's complement format. two?s complement format: lsb is 0.25mv. range is +/-32mv r76 (4ch) dc servo 9 7:0 dcs_dac_wr_v al0 [7:0] 0000 0000 dc offset value for hpoutl in dac write dc servo mode in two's complement format. in readback, the current dc offset value is returned in two's complement format. two?s complement format: lsb is 0.25mv. range is +/-32mv r77 (4dh) dc servo readback 0 11:8 dcs_cal_comp lete [3:0] 0000 dc servo complete status [3] - lineoutr [2] - lineoutl [1] - hpoutr [0] - hpoutl 0 = dac write or start-up dc servo mode not completed. 1 = dac write or start-up dc servo mode complete.
WM8904 pre-production w pp, rev 3.3, september 2012 88 register address bit label default description 7:4 dcs_dac_wr_c omplete [3:0] 0000 dc servo dac write status [3] - lineoutr [2] - lineoutl [1] - hpoutr [0] - hpoutl 0 = dac write dc servo mode not completed. 1 = dac write dc servo mode complete. 3:0 dcs_startup_ complete [3:0] 0000 dc servo start-up status [3] - lineoutr [2] - lineoutl [1] - hpoutr [0] - hpoutl 0 = start-up dc servo mode not completed.. 1 = start-up dc servo mode complete. table 52 dc servo enable and start-up modes dc servo active modes the dc servo modes described above are suitable for initialising the dc offset correction circuit on the line and headphone outputs as part of a controll ed start-up sequence which is executed before the signal path is fully enabled. addi tional modes are avail able for use whilst the signal path is active; these modes may be of benefit following a large c hange in signal gain, which can lead to a change in dc offset level. periodic updates may also be desirable to remove slow drifts in dc offset caused by changes in parameters such as device temperature. the dc servo circuit is enabled on hpoutr and hpoutl by setting dcs_ena_chan_1 and dcs_ena_chan_0 respectively, as described earlier in table 52. similarly, the dc servo circuit is enabled on lineoutr and lineoutl by se tting dcs_ena_chan_3 and dcs_ena_chan_2 respectively. writing a logic 1 to dcs_trig_single_ n initiates a single dc offset measurement and adjustment to the associated output; (?n? = 3 for lineoutr channel, 2 for lineoutl channel, 1 for hpoutr channel, 0 for hpoutl channel). this will adjust the dc offset correction on the selected channel by no more than 1lsb (0.25mv). setting dcs_timer_period_01 or dcs_timer_per iod_23 to a non-zero value will cause a single dc offset measurement and adjustment to be scheduled on a periodic basis. periodic rates ranging from every 0.52s to in excess of 2 hours can be selected. writing a logic 1 to dcs_trig_series_ n initiates a series of dc offset measurements and applies the necessary correction to the associated outpu t. the number of dc servo operations performed is determined by dcs_series_no_01 or dcs_seri es_no_23. a maximum of 128 operations may be selected, though a much lower value will be sufficient in most applications. the dc servo control fields associated with active modes (suitable for use on a signal path that is in active use) are described in table 53.
pre-production WM8904 w pp, rev 3.3, september 2012 89 register address bit label default description r68 (44h) dc servo 1 15 dcs_trig_sing le_3 0 writing 1 to this bit selects a single dc offset correction for lineoutr. in readback, a value of 1 indicates that the dc servo single correction is in progress. 14 dcs_trig_sing le_2 0 writing 1 to this bit selects a single dc offset correction for lineoutl. in readback, a value of 1 indicates that the dc servo single correction is in progress. 13 dcs_trig_sing le_1 0 writing 1 to this bit selects a single dc offset correction for hpoutr. in readback, a value of 1 indicates that the dc servo single correction is in progress. 12 dcs_trig_sing le_0 0 writing 1 to this bit selects a single dc offset correction for hpoutl. in readback, a value of 1 indicates that the dc servo single correction is in progress. 11 dcs_trig_seri es_3 0 writing 1 to this bit selects a series of dc offset corrections for lineoutr. in readback, a value of 1 indicates that the dc servo dac write correction is in progress. 10 dcs_trig_seri es_2 0 writing 1 to this bit selects a series of dc offset corrections for lineoutl. in readback, a value of 1 indicates that the dc servo dac write correction is in progress. 9 dcs_trig_seri es_1 0 writing 1 to this bit selects a series of dc offset corrections for hpoutr. in readback, a value of 1 indicates that the dc servo dac write correction is in progress. 8 dcs_trig_seri es_0 0 writing 1 to this bit selects a series of dc offset corrections for hpoutl. in readback, a value of 1 indicates that the dc servo dac write correction is in progress. r71 (47h) dc servo 4 6:0 dcs_series_n o_23 [6:0] 010_1010 number of dc servo updates to perform in a series event for lineoutl/lineoutr. 0 = 1 updates 1 = 2 updates ... 127 = 128 updates r72 (48h) dc servo 5 6:0 dcs_series_n o_01 [6:0] 010 1010 number of dc servo updates to perform in a series event for hpoutl/hpoutr. 0 = 1 updates 1 = 2 updates ... 127 = 128 updates
WM8904 pre-production w pp, rev 3.3, september 2012 90 register address bit label default description r69 (45h) dc servo 2 11:8 dcs_timer_pe riod_23 [3:0] 1010 time between periodic updates for lineoutl/lineoutr. time is calculated as 0.256s x (2^period) 0000 = off 0001 = 0.52s 1010 = 266s (4min 26s) 1111 = 8519s (2hr 22s) 3:0 dcs_timer_pe riod_01 [3:0] 1010 time between periodic updates for hpoutl/hpoutr. time is calculated as 0.256s x (2^period) 0000 = off 0001 = 0.52s 1010 = 266s (4min 26s) 1111 = 8519s (2hr 22s) table 53 dc servo active modes dc servo readback the current dc offset value for each line and headphone output channel can be read in two?s complement format from the dcs_dac_wr_val_n [7:0 ] bit fields in registers r73, r74, r75 and r76. note that these values may form the basis of settings that are subsequently used by the dc servo in dac write mode. digital audio interface the digital audio interface is used for inpu tting dac data to the WM8904 and outputting adc data from it. the digital audio in terface uses four pins: ? adcdat: adc data output ? dacdat: dac data input ? lrclk: left/right data alignment clock ? bclk: bit clock, for synchronisation the clock signals bclk and lrclk can be outputs when the WM8904 operates as a master, or inputs when it is a slave (see ?maste r and slave mode operation?, below). four different audio data formats are supported: ? left justified ? right justified ? i2s ? dsp mode all four of these modes are msb first. they are described in ?audio data formats (normal mode)?, below. refer to the ?signal timing require ments? section for timing information. time division multiplexing (tdm) is available in all four data format modes. the WM8904 can be programmed to send and receive data in one of two time slots. pcm operation is supported using the dsp mode.
pre-production WM8904 w pp, rev 3.3, september 2012 91 master and slave mode operation the WM8904 digital audio interface can operate in ma ster or slave mode, as shown in figure 40 and figure 41. figure 40 master mode figure 41 slave mode in master mode, bclk is derived from sysclk via a programmable division set by bclk_div. in master mode, lrclk is derived from bclk via a programmable division set by lrclk_rate. the bclk input to this divider may be internal or external, allowing mixed master and slave modes. the direction of these signals and the clock frequencie s are controlled as described in the ?digital audio interface control? section. bclk and lrclk can be enabled as outputs in slave mode, allowing mixed master/slave operation - see ?digital audio interface control?. operation with tdm time division multiplexing (tdm) allows multiple devices to transfer data simultaneously on the same bus. the WM8904 adcs and dacs support tdm in ma ster and slave modes for all data formats and word lengths. tdm is enabled and confi gured using register bits defined in the ?digital audio interface control? section. WM8904 processor WM8904 or similar codec adcdat lrclk dacdat bclk adcdat lrclk dacdat bclk WM8904 processor WM8904 or similar codec adcdat lrclk dacdat bclk adcdat lrclk dacdat bclk figure 42 tdm with WM8904 as master figure 43 tdm with other codec as master
WM8904 pre-production w pp, rev 3.3, september 2012 92 WM8904 processor WM8904 or similar codec adcdat lrclk dacdat bclk adcdat lrclk dacdat bclk figure 44 tdm with processor as master note: the WM8904 is a 24-bit device. if the user operates the WM8904 in 32-bit mode then the 8 lsbs will be ignored on the receiving side and not driven on the transmitting side. it is therefore recommended to add a pull-down resistor if necessary to the dacdat line and the adcdat line in tdm mode. bclk frequency the bclk frequency is controlled relative to sysclk by the bclk_div divider. internal clock divide and phase control mechanisms ensure that the bc lk and lrclk edges will occur in a predictable and repeatable position relative to each other and rela tive to the data for a given combination of dac/adc sample rate and bclk_div settings. bclk_div is defined in the ?digital audio interf ace control? section. see also the ?clocking and sample rates? section for more information. audio data formats (normal mode) in right justified mode, the lsb is availabl e on the last rising edge of bclk before a lrclk transition. all other bits are transmitted bef ore (msb first). depending on word length, bclk frequency and sample rate, there may be unused bc lk cycles after each lrclk transition. figure 45 right justified audio interface (assuming n-bit word length)
pre-production WM8904 w pp, rev 3.3, september 2012 93 in left justified mode, the msb is available on the first rising edge of bclk following a lrclk transition. the other bits up to the lsb are then transmitted in order. depending on word length, bclk frequency and sample rate, there may be unused bclk cycles before each lrclk transition. figure 46 left justified audio interface (assuming n-bit word length) in i 2 s mode, the msb is available on the second ri sing edge of bclk following a lrclk transition. the other bits up to the lsb are then transmi tted in order. depending on word length, bclk frequency and sample rate, there may be unused bclk cycles between the lsb of one sample and the msb of the next. n n-1 n-2 3 2 1 n n-1 n-2 3 2 1 left channel right channel msb lsb input word length (wl) 1/fs lrclk bclk dacdat/ adcdat 1 bclk 1 bclk figure 47 i2s justified audio interface (assuming n-bit word length) in dsp mode, the left channel msb is available on either the 1 st (mode b) or 2 nd (mode a) rising edge of bclk (selectable by aif_lrclk_inv) fo llowing a rising edge of lrclk. right channel data immediately follows left channel data. depending on word length, bclk frequency and sample rate, there may be unused bclk cycles between the lsb of the right channel data and the next sample. in device master mode, the lrclk output will resemble the frame pulse shown in figure 48 and figure 49. in device slave mode, figure 50 and figure 51, it is possi ble to use any length of frame pulse less than 1/fs, providing the falling edge of the frame pulse occurs greater than one bclk period before the rising edge of the next frame pulse.
WM8904 pre-production w pp, rev 3.3, september 2012 94 figure 48 dsp mode audio interface (mode a, aif_lrclk_inv=0, master) figure 49 dsp mode audio interface (mode b, aif_lrclk_inv=1, master) figure 50 dsp mode audio interface (mode a, aif_lrclk_inv=0, slave) figure 51 dsp mode audio interface (mode b, aif_lrclk_inv=1, slave)
pre-production WM8904 w pp, rev 3.3, september 2012 95 pcm operation is supported in dsp interface mode. WM8904 adc data that is output on the left channel will be read as mono pcm data by the receiving equipment. mono pcm data received by the WM8904 will be treated as left channel data. this dat a may be routed to the left/right dacs as described in the ?digital mixing? section. audio data formats (tdm mode) tdm is supported in master and slave mode and is enabled by register bits aifadc_tdm and aifdac_tdm. all audio interface data formats suppor t time division multiplexing (tdm) for adc and dac data. two time slots are available (slot 0 and slot 1) , selected by register bits aifadc_tdm_chan and aifdac_tdm_chan which control time slots for the adc data and the dac data. when tdm is enabled, the adcdat pin will be tri-st ated immediately before and immediately after data transmission, to allow another audio device to dr ive this signal line for the remainder of the sample period. it is important that two audio devices do not attempt to drive the data pin simultaneously, as this could result in a short circ uit. see ?audio interface ti ming? for details of the adcdat output relative to bclk signal. note that it is possible to ensure a gap exists between transmissions by setting the transmi tted word length to a value higher than the actual length of the data. for example, if 32-bit word length is sele cted where only 24-bit data is available, then the WM8904 interface will tri-state after transmission of t he 24-bit data; this creates an 8-bit gap after the WM8904?s tdm transmission slot. when tdm is enabled, bclk frequency must be high enough to allow data from both time slots to be transferred. the relative timing of slot 0 and sl ot 1 depends upon the selected data format as shown in figure 52 to figure 56. figure 52 tdm in right-justified mode figure 53 tdm in left-justified mode
WM8904 pre-production w pp, rev 3.3, september 2012 96 figure 54 tdm in i 2 s mode 1/fs lrclk bclk dacdat/ adcdat 1 bclk slot 0 left slot 0 right slot 1 left slot 1 right falling edge can occur anywhere in this area 1 bclk figure 55 tdm in dsp mode a figure 56 tdm in dsp mode b
pre-production WM8904 w pp, rev 3.3, september 2012 97 digital audio interface control the register bits controlling audio data format, wo rd length, left/right channel data source and tdm are summarised in table 54. register address bit label default description r24 (18h) audio interface 0 7 aifadcl_sr c 0 left digital audio channel source 0 = left adc data is output on left channel 1 = right adc data is output on left channel 6 aifadcr_sr c 1 right digital audio channel source 0 = left adc data is output on right channel 1 = right adc data is output on right channel 5 aifdacl_sr c 0 left dac data source select 0 = left dac outputs left channel data 1 = left dac outputs right channel data 4 aifdacr_sr c 1 right dac data source select 0 = right dac outputs left channel data 1 = right dac outputs right channel data r25 (19h) audio interface 1 13 aifdac_tdm 0 dac tdm enable 0 = normal dacdat operation 1 = tdm enabled on dacdat 12 aifdac_tdm _chan 0 dacdat tdm channel select 0 = dacdat data input on slot 0 1 = dacdat data input on slot 1 11 aifadc_tdm 0 adc tdm enable 0 = normal adcdat operation 1 = tdm enabled on adcdat 10 aifadc_tdm _chan 0 adcdat tdm channel select 0 = adcdat outputs data on slot 0 1 = adcdat output data on slot 1 7 aif_bclk_in v 0 bclk invert 0 = bclk not inverted 1 = bclk inverted 4 aif_lrclk_i nv 0 lrc polarity / dsp mode a-b select. right, left and i2s modes ? lrc polarity 0 = not inverted 1 = inverted dsp mode ? mode a-b select 0 = msb is available on 2nd bclk rising edge after lrc rising edge (mode a) 1 = msb is available on 1st bclk rising edge after lrc rising edge (mode b) 3:2 aif_wl [1:0] 10 digital audio interface word length 00 = 16 bits 01 = 20 bits 10 = 24 bits 11 = 32 bits 1:0 aif_fmt [1:0] 10 digital audio interface format 00 = right justified 01 = left justified 10 = i2s 11 = dsp table 54 digital audio interface data control
WM8904 pre-production w pp, rev 3.3, september 2012 98 note that the WM8904 is a 24-bit device. in 32-bi t mode (aif_wl=11), the 8 lsbs are ignored on the receiving side and not driv en on the transmitting side. audio interface output tri-state register bit aif_tris can be used to tri-state the audio interface pins as described in table 55. all digital audio interface pins will be tri-stated by this function, regardless of the state of other registers which control these pin configurations. register address bit label default description r25 (19h) audio interface 1 8 aif_tris 0 audio interface tristate 0 = audio interface pins operate normally 1 = tristate all audio interface pins table 55 digital audio interface tri-state control bclk and lrclk control the audio interface can be programmed to operat e in master mode or slave mode using the bclk_dir and lrclk_dir register bits. in master mode, the bclk and lrclk signals are generated by the WM8904 when any of the adcs or dacs is enabled. in slave mode, the bclk and lrclk clock outputs are disabled by default to allo w another digital audio interface to drive these pins. it is also possible to force the bclk or lrclk signals to be output using bclk_dir and lrclk_dir, allowing mixed master and slave m odes. the bclk_dir and lrclk_dir fields are defined in table 56. register address bit label default description r25 (19h) audio interface 1 6 bclk_dir 0 audio interface bclk direction 0 = bclk is input 1 = bclk is output r26 (1ah) audio interface 2 4:0 bclk_div [4:0] 0_0100 bclk frequency (master mode) 00000 = sysclk 00001 = sysclk / 1.5 00010 = sysclk / 2 00011 = sysclk / 3 00100 = sysclk / 4 (default) 00101 = sysclk / 5 00110 = sysclk / 5.5 00111 = sysclk / 6 01000 = sysclk / 8 01001 = sysclk / 10 01010 = sysclk / 11 01011 = sysclk / 12 01100 = sysclk / 16 01101 = sysclk / 20 01110 = sysclk / 22 01111 = sysclk / 24 10000 = sysclk / 25 10001 = sysclk / 30 10010 = sysclk / 32 10011 = sysclk / 44 10100 = sysclk / 48
pre-production WM8904 w pp, rev 3.3, september 2012 99 register address bit label default description r27 (1bh) audio interface 3 11 lrclk_dir 0 audio interface lrc direction 0 = lrc is input 1 = lrc is output 10:0 lrclk_rate [10:0] 000_0100 _0000 lrc rate (master mode) lrc clock output = bclk / lrclk_rate integer (lsb = 1) valid range: 8 to 2047 table 56 digital audio interface clock control companding the WM8904 supports a-law and ? -law companding on both transmit (adc) and receive (dac) sides as shown in table 57. register address bit label default description r24 (18h) audio interface 0 3 adc_comp 0 adc companding enable 0 = disabled 1 = enabled 2 adc_compmode 0 adc companding type 0 = -law 1 = a-law 1 dac_comp 0 dac companding enable 0 = disabled 1 = enabled 0 dac_compmode 0 dac companding type 0 = -law 1 = a-law table 57 companding control companding involves using a piecew ise linear approximation of the following equations (as set out by itu-t g.711 standard) for data compression: ? -law (where ? =255 for the u.s. and japan): f(x) = ln( 1 + ? |x|) / ln( 1 + ? ) -1 x 1 a-law (where a=87.6 for europe): f(x) = a|x| / ( 1 + lna) x 1/a f(x) = ( 1 + lna|x|) / (1 + lna) 1/a x 1 the companded data is also inverted as recommended by the g.711 standard (all 8 bits are inverted for ? -law, all even data bits are inverted for a-law). the data will be transmitted as the first 8 msbs of data. companding converts 13 bits ( ? -law) or 12 bits (a-law) to 8 bits using non-linear quantization. this provides greater precision for low amplitude signals than for high amplitude signals, resulting in a greater usable dynamic range than 8 bit linear quant ization. the companded signal is an 8-bit word comprising sign (1 bit), exponent (3 bits) and mantissa (4 bits). 8-bit mode is selected whenever dac_comp=1 or adc_comp=1. the use of 8-bit data allows samples to be passed using as few as 8 bclk cy cles per lrclk frame. when using dsp mode b, 8-bit data words may be transferred c onsecutively every 8 bclk cycles.
WM8904 pre-production w pp, rev 3.3, september 2012 100 8-bit mode (without companding) may be enabled by setting dac_compmode=1 or adc_compmode=1, when dac_comp=0 and adc_comp=0. bit7 bit [6:4] bit [3:0] sign exponent mantissa table 58 8-bit companded word composition u-law companding 0 20 40 60 80 100 120 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 normalised input companded output 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 normalised output figure 57 -law companding a-law companding 0 20 40 60 80 100 120 0 0.2 0.4 0.6 0.8 1 normalised input companded output 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 normalised output figure 58 a-law companding
pre-production WM8904 w pp, rev 3.3, september 2012 101 loopback setting the loopback register bit enables digital l oopback. when this bit is set, the adc digital data output is routed to the dac digital data input path. the digital audio interface input (dacdat) is not used when loopback is enabled. register address bit label default description r24 (18h) audio interface 0 8 loopback 0 digital loopback function 0 = no loopback 1 = loopback enabled (adc data output is directly input to dac data input). table 59 loopback control note: when the digital sidetone is enabled, adc data will also be added to dac digital data input path within the digital mixing circuit. this app lies regardless of whether loopback is enabled. digital pull-up and pull-down the WM8904 provides integrated pull-up and pull-dow n resistors on each of the mclk, dacdat, lrclk and bclk pins. this provides a flexible capability for interfacing with other devices. each of the pull-up and pull-down resistors can be configur ed independently using the register bits described in table 60. register address bit label default description r126 (7eh) digital pulls 7 mclk_pu 0 mclk pull-up resistor enable 0 = pull-up disabled 1 = pull-up enabled 6 mclk_pd 0 mclk pull-down resistor enable 0 = pull-down disabled 1 = pull-down enabled 5 dacdat_pu 0 dacdat pull-up resistor enable 0 = pull-up disabled 1 = pull-up enabled 4 dacdat_pd 0 dacdat pull-down resistor enable 0 = pull-down disabled 1 = pull-down enabled 3 lrclk_pu 0 lrclk pull-up resistor enable 0 = pull-up disabled 1 = pull-up enabled 2 lrclk_pd 0 lrclk pull-down resistor enable 0 = pull-down disabled 1 = pull-down enabled 1 bclk_pu 0 bclk pull-up resistor enable 0 = pull-up disabled 1 = pull-up enabled 0 bclk_pd 0 bclk pull-down resistor enable 0 = pull-down disabled 1 = pull-down enabled table 60 digital audio interface pull-up and pull-down control
WM8904 pre-production w pp, rev 3.3, september 2012 102 clocking and sample rates the internal clocks for the WM8904 are all derived from a common internal clock source, sysclk. this clock is the reference for the adcs, dacs, d sp core functions, digital audio interface, dc servo control and other internal functions. sysclk can either be derived directly from mclk, or may be generated from a frequency locked loop (fll) using mclk, bclk or lrclk as a refe rence. many commonly-used audio sample rates can be derived directly from typical mclk frequencie s; the fll provides additional flexibility for a wide range of mclk frequencies. to avoid audible glit ches, all clock configurations must be set up before enabling playback. the fll can be used to generate a free-running clock in the absence of an external reference source; see ?frequenc y locked loop (fll)? for further details. the WM8904 supports automatic clocking configurati on. the programmable dividers associated with the adcs, dacs, dsp core functions and dc serv o are configured automatically, with values determined from the clk_sys_rate and sample_rate fields. the user must also configure the opclk (if required), the toclk (if requi red) and the digital audio interface. oversample rates of 64fs or 128fs are supported (based on a 48khz sample rate). a 256khz clock, supporting a number of inte rnal functions, is derived from sysclk. the dc servo control is clocked from sysclk. a gpio clock, opclk, can be derived from sysc lk and output on a gpio pin to provide clocking to other devices. this clock is enabled by opclk_ena and controlled by opclk_div. a slow clock, toclk, is used to de-bounce the butt on/accessory detect inputs, and to set the timeout period for volume updates when zero-cross detect is used. this clock is enabled by toclk_ena and controlled by toclk_rate, tocl k_rate_x4 and toclk_rate_div16. in master mode, bclk is derived from sysclk via a programmable divider set by bclk_div. in master mode, the lrclk is derived from bclk via a programmable divider lrclk_rate. the lrclk can be derived from an internal or exter nal bclk source, allowing mixed master/slave operation. the control registers associated with clocking and sa mple rates are shown in table 61 to table 65. the overall clocking scheme for the WM8904 is illustrated in figure 59.
pre-production WM8904 w pp, rev 3.3, september 2012 103 mclk fll f ref f out f/n fll fll_clk_ref_src selects the input reference for fll oscillator. sysclk internal clocks are derived from sysclk. these are enabled by clk_sys_ena. sysclk can be derived from mclk or from the fll output. the sysclk source is selected by sysclk_src and has a divide by 2 option (mclkdiv). clk_dsp dsp clocks are derived from clk_sys. these are enabled by clk_dsp_ena. dac clocks dac dsp clock is derived from dsp_clk automatically. alternate settings are available using dac_osr128. adc clocks adc dsp clock is derived from dsp_clk automatically. alternate settings are available using adc_osr128. dc servo clock the dc servo clock is derived from sysclk automatically. 256khz clock the 256khz clock for the charge pump, control write sequencer and other internal functions is derived from sysclk automatically toclk control the slow clock for volume update timeout and gpio / accessory detect de-bounce is enabled by toclk_ena. the frequency is set by toclk_rate, toclk_rate_div16 and toclk_rate_x4. opclk output gpio output clock frequency is set by opclk_div. lrclk rate lrclk rate is set by lrclk_rate in master mode. the bclk input to this divider may be internal or external. bclk rate bclk rate is set by bclk_div in master mode. sysclk_src clk_sys_ena fll_clk_ ref_src r14h[0] mclk_div 0 = mclk 1 = mclk / 2 clk_dsp_ena clk_dsp 64fs or 128fs f/n adc f/n r0ah[0] adc_osr128 0 = f / 4 (64fs) 1 = f / 2 (128fs) dac f/n automatic dsp clocking control sample_rate [2:0] clk_sys_rate [3:0] the dac, adc, 256khz, and dc servo clocks are configured automatically according to sample_rate and clk_sys_rate. sysclk dac_osr128 f/n dc servo clock gpio clock output f/n opclk_div r1ah[11:8] opclk_div[3:0] 0000 = sysclk 0001 = sysclk / 2 0010 = sysclk / 3 0011 = sysclk / 4 0100 = sysclk / 5.5 0101 = sysclk / 6 0110 = sysclk / 8 0111 = sysclk / 12 1000 = sysclk / 16 1001 to 1111 = reserved opclk_ena f/n 256khz clock to charge pump, control write sequencer and other circuits f.n toclk_ena button/accessory detect de-bounce, volume update timeout f/n f/1024 r14h[13] toclk_rate_x4 0 = f x 1 1 = f x 4 r16h[12] toclk_rate 0 = f / 2 1 = f / 1 r1ah[4:0] bclk_div[4:0] (master mode) 00000 = sysclk 00001 = sysclk / 1.5 00010 = sysclk / 2 00011 = sysclk / 3 00100 = sysclk / 4 00101 = sysclk / 5 00110 = sysclk / 5.5 00111 = sysclk / 6 01000 = sysclk / 8 01001 = sysclk / 10 01010 = sysclk / 11 01011 = sysclk / 12 01100 = sysclk / 16 01101 = sysclk / 20 01110 = sysclk / 22 bclk_div [3:0] lrclk_rate [10:0] lrclk bclk mclk_inv f/n r14h[14] toclk_rate_div16 0 = f / 1 1 = f / 16 bclk lrclk adc_osr128 f/n r21h[6] dac_osr128 0 = low power (normal osr) 1 = high performance (double osr) bclk_dir lrclk_dir f/n master mode clock outputs f/n figure 59 clocking overview sysclk control the sysclk_src bit is used to select the source for sysclk. the source may be either the mclk input or the fll output. the mclk input can be inverted or non-inverted, as selected by the mclk_inv bit. the selected source may also be adjusted by the mclk_div divider to generate sysclk. these register fields are described in table 61. see ?frequency locked loop (fll)? for more details of the frequency locked loop clock generator. the sysclk signal is enabled by register bit cl k_sys_ena. this bit should be set to 0 when reconfiguring clock sources. it is not recommended to change sysclk_src while the clk_sys_ena bit is set.
WM8904 pre-production w pp, rev 3.3, september 2012 104 the following operating frequency limits must be obs erved when configuring sysclk. failure to observe these limits will result in degraded noise performance and/or incorrect adc/dac functionality. ? sysclk ? 3mhz ? if dac_osr128 = 1 then sysclk ? 6mhz ? if dac_mono = 1, then sysclk ? 64 x fs ? if dac_mono = 0, then sysclk ? 128 x fs ? if adcl_ena = 1 or adcr_ena = 1 then sysclk ? 256 x fs note that dac mono mode (dac_mono = 1) is only valid when one or other dac is disabled. if both dacs are enabled, then the minimum sysclk for clocking the dacs is 128 x fs. the sysclk control register fi elds are defined in table 61. register address bit label default description r22 (16h) clock rates 2 15 mclk_inv 0 mclk invert 0 = mclk not inverted 1 = mclk inverted 14 sysclk_src 0 sysclk source select 0 = mclk 1 = fll output 2 clk_sys_ena 0 system clock enable 0 = disabled 1 = enabled r20 (14h) clock rates 0 0 mclk_div 0 enables divide by 2 on mclk 0 = sysclk = mclk 1 = sysclk = mclk / 2 table 61 mclk and sysclk control control interface clocking register map access is possible with or without a master clock (mclk). however, if clk_sys_ena has been set to 1, then a master clock must be pres ent for control register read/write operations. if clk_sys_ena = 1 and mclk is not present, then r egister access will be unsuccessful. (note that read/write access to register r22, contai ning clk_sys_ena, is always possible.) if it cannot be assured that mclk is present when a ccessing the register map, then it is required to set clk_sys_ena = 0 to ensure correct operation. it is possible to use the WM8904 analogue bypass paths to the differential line outputs (lon/lop and ron/rop) without mclk. note that mclk is always required when using hpoutl, hpoutr, lineoutl or lineoutr. clocking configuration the WM8904 supports a wide range of standard audio sample rates from 8khz to 48khz. the automatic clocking configuration simplifies the conf iguration of the clock dividers in the WM8904 by deriving most of the necessary parameters fr om a minimum number of user registers. the sample_rate field selects the sample rate, fs, of the adc and dac. note that the same sample rate always applies to the adc and dac. the clk_sys_rate field must be set according to t he ratio of sysclk to fs . when these fields are set correctly, the sample rate decoder circuit autom atically determines the clocking configuration for all other circuits within the WM8904.
pre-production WM8904 w pp, rev 3.3, september 2012 105 a high performance mode of dac operation can be selected by setting the dac_osr128 bit; in 48khz sample mode, the dac_osr128 feature resu lts in 128x oversampling. audio performance is improved, but power consumption is also increased. register address bit label default description r33 (21h) dac digital 1 6 dac_osr128 0 dac oversample rate select 0 = low power (normal osr) 1 = high performance (double osr) r21 (15h) clock rates 1 13:10 clk_sys_rat e [3:0] 0011 selects the sysclk / fs ratio 0000 = 64 0001 = 128 0010 = 192 0011 = 256 0100 = 384 0101 = 512 0110 = 768 0111 = 1024 1000 = 1408 1001 = 1536 2:0 sample_rate [2:0] 101 selects the sample rate (fs) 000 = 8khz 001 = 11.025khz, 12khz 010 = 16khz 011 = 22.05khz, 24khz 100 = 32khz 101 = 44.1khz, 48khz 110 to 111 = reserved table 62 automatic clocking configuration control adc / dac clock control the clocking of the adc and dac circuits is derived from clk_dsp, which is enabled by clk_dsp_ena. clk_dsp is generated from sysc lk which is separately enabled, using the register bit clk_sys_ena. two modes of adc operation can be selected usi ng the adc_osr128 bit; in 48khz sample mode, setting the adc_osr128 bit results in 128x oversa mpling. this bit is enabl ed by default, giving best audio performance. deselecting this bit gives 64x oversampling in 48khz mode, resulting in decreased power consumption. higher performance dac operation c an be achieved by increasing the dac oversample rate - see table 62. the adc / dac clock control registers are defined in table 63. register address bit label default description r10 (0ah) analog adc 0 0 adc_osr128 1 adc oversampling ratio 0 = low power (64 x fs) 1 = high performance (128 x fs) r22 (16h) clock rates 2 1 clk_dsp_ena 0 dsp clock enable 0 = disabled 1 = enabled table 63 adc / dac clock control
WM8904 pre-production w pp, rev 3.3, september 2012 106 opclk control a clock output (opclk) derived from sysclk may be output on a gpio pin. this clock is enabled by register bit opclk_ena, and its frequency is controlled by opclk_div. this output of this clock is also dependent upon t he gpio register settings described under ?general purpose input/output (gpio)?. register address bit label default description r22 (16h) clock rates 2 3 opclk_ena 0 gpio clock output enable 0 = disabled 1 = enabled r26 (1ah) audio interface 2 11:8 opclk_div [3:0] 0000 gpio output clock divider 0000 = sysclk 0001 = sysclk / 2 0010 = sysclk / 3 0011 = sysclk / 4 0100 = sysclk / 5.5 0101 = sysclk / 6 0110 = sysclk / 8 0111 = sysclk / 12 1000 = sysclk / 16 1001 to 1111 = reserved table 64 opclk control toclk control a slow clock (toclk) is derived from the in ternally generated 256khz clock to enable input de- bouncing and volume update timeout functions. this clock is enabled by register bit toclk_ena, and its frequency is controlled by toclk_rate and toclk_rate_x4, as described in table 65. register address bit label default description r22 (16h) clock rates 2 12 toclk_rate 0 toclk rate divider (/2) 0 = f / 2 1 = f / 1 0 toclk_ena 0 zero cross timeout enable 0 = disabled 1 = enabled r20 (14h) clock rates 0 14 toclk_rate_ div16 0 toclk rate divider (/16) 0 = f / 1 1 = f / 16 13 toclk_rate_ x4 0 toclk rate multiplier 0 = f x 1 1 = f x 4 table 65 toclk control
pre-production WM8904 w pp, rev 3.3, september 2012 107 a list of possible toclk rates is provided in table 66. toclk_rate toclk_rate_x4 toclk_rate_div16 toclk freq (hz) period (ms) 1 1 0 1000 1 0 1 0 500 2 1 0 0 250 4 0 0 0 125 8 1 1 1 62.5 16 0 1 1 31.25 32 1 0 1 15.625 64 0 0 1 7.8125 128 table 66 toclk rates adc / dac operation at 88.2k / 96k the WM8904 supports adc or dac operation at 88.2k hz and 96khz sample rates. this section details specific conditions app licable to these operating modes. note that simultaneous adc and dac operation at 88.2khz or 96khz is not possible. for dac operation at 88.2khz or 96khz sample ra tes, the available clocking configurations are detailed in table 67. dac operation at these samp le rates is achieved by setting the sample_rate field to half the required sample rate (eg. select 48khz for 96khz mode). for dac operation at 88.2khz or 96khz sample ra tes, the adcs must both be disabled (adcl_ena = 0 and adcr_ena = 0). also, the dac_osr128 register must be set to 0. retune tm mobile can not be used during 88.2khz or 96khz operat ion, so eq_ena must be set to 0. the sysclk frequency is derived from mclk. t he maximum mclk frequency is defined in the ?signal timing requirements? section. sample rate register configuration clocking ratio 88.2khz sample_rate = 101 clk_sys_rate = 0001 (sysclk / fs = 128) bclk_div = 00010 lrclk_rate = 040h sysclk = 128 x fs 96khz sample_rate = 101 clk_sys_rate = 0001 (sysclk / fs = 128) bclk_div = 00010 lrclk_rate = 040h sysclk = 128 x fs table 67 dac operation at 88.2khz and 96khz sample rates for adc operation at 88.2khz or 96khz sample ra tes, the available clo cking configurations are detailed in table 68. adc operation at these sample rates is achiev ed by setting the sample_rate field to half the required sample rate (eg. select 48khz for 96k hz mode). for adc operati on at 88.2khz or 96khz sample rates, the dacs must both be disabled (dacl_ena = 0 and dacr_ena = 0). note that adc_osr128, adc_128_osr_tst_mode, and adc_biasx1p5 must be configured according to table 68. the sysclk frequency is derived from mclk. t he maximum mclk frequency is defined in the ?signal timing requirements? section.
WM8904 pre-production w pp, rev 3.3, september 2012 108 sample rate register configuration clocking ratio 88.2khz sample_rate = 101 clk_sys_rate = 0001 (sysclk / fs = 128) bclk_div = 00010 lrclk_rate = 040h adc_osr128 = 0 adc_128_osr_tst_mode = 0 adc_biasx1p5 = 0 sysclk = 128 x fs 96khz sample_rate = 101 clk_sys_rate = 0001 (sysclk / fs = 128) bclk_div = 00010 lrclk_rate = 040h adc_osr128 = 0 adc_128_osr_tst_mode = 0 adc_biasx1p5 = 0 sysclk = 128 x fs table 68 adc operation at 88.2khz and 96khz sample rates frequency locked loop (fll) the integrated fll can be used to generate sysclk from a wide variety of different reference sources and frequencies. the fll can use either mclk , bclk or lrclk as its reference, which may be a high frequency (eg. 12.288mhz) or low frequency (eg. 32,768khz) reference. the fll is tolerant of jitter and may be used to generate a stable sysc lk from a less stable input signal. the fll characteristics are summarised in ?electrical characteristics?. note that the fll can be used to generate a fr ee-running clock in the absence of an external reference source. this is described in t he ?free-running fll clock? section below. the fll is enabled using the fll_ena register bi t. note that, when changing fll settings, it is recommended that the digital circ uit be disabled via fll_ena and then re-enabled after the other register settings have been updated. when changing the input reference frequency f ref , it is recommended the fll be reset by setting fll_ena to 0. the fll_clk_ref_src field allows mclk, bclk or lrclk to be selected as the input reference clock. the field fll_clk_ref_div provi des the option to divide the input reference (mclk, bclk or lrclk) by 1, 2, 4 or 8. this field should be set to bring the reference down to 13.5mhz or below. for best performance, it is recommended that the highes t possible frequency - within the 13.5mhz limit - should be selected. the field fll_ctrl_rate controls in ternal functions within the fll; it is recommended that only the default setting be used for this parameter. fll_gain c ontrols the internal loop gain and should be set to the recommended value quoted in table 71. the fll output frequency is directly determined from fll_fratio, fll_outdiv and the real number represented by fll_n and fll_k. the field fll_n is an integer (lsb = 1); fll_k is the fractional portion of the number (msb = 0.5). the fr actional portion is only va lid in fractional mode when enabled by the field fll_fracn_ena. it is recommended that fll_fracn_ena is enabled at a ll times. power consumption in the fll is reduced in integer mode; however, the performance may also be reduced, with increased noise or jitter on the output. if low power consumption is required, then fll se ttings must be chosen when n.k is an integer (ie. fll_k = 0). in this case, the fractional m ode can be disabled by setting fll_fracn_ena = 0. for best fll performance, a non-integer value of n.k is required. in this case, the fractional mode must be enabled by setting fll_fracn_ena = 1. the fll settings must be adjusted, if necessary, to produce a non-integer value of n.k.
pre-production WM8904 w pp, rev 3.3, september 2012 109 the fll output frequency is generated according to the following equation: f out = (f vco / fll_outdiv) the fll operating frequency, f vco is set according to the following equation: f vco = (f ref x n.k x fll_fratio) see table 71 for the coding of t he fll_outdiv and fll_fratio fields. f ref is the input frequency, as determined by fll_clk_ref_div. f vco must be in the range 90-100 mhz. frequencies outside this range cannot be supported. note that the output frequencies that do not lie within the ranges quoted above cannot be guaranteed across the full range of device operating temperatures. in order to follow the above requirements for f vco , the value of fll_outdiv should be selected according to the desired output f out . the divider, fll_outdiv, must be set so that f vco is in the range 90-100mhz. the available divi sions are integers from 4 to 64. some typical settings of fll_outdiv are noted in table 69. output frequency f out fll_outdiv 2.8125 mhz - 3.125 mhz 011111 (divide by 32) 3.75 mhz - 4.1667 mhz 011000 (divide by 24) 5.625 mhz - 6.25 mhz 001111 (divide by 16) 11.25 mhz - 12.5 mhz 000111 (divide by 8) 18 mhz - 20 mhz 000100 (divide by 5) 22.5 mhz - 25 mhz 000011 (divide by 4) table 69 selection of fll_outdiv the value of fll_fratio should be selected as described in table 70. reference frequency f ref fll_fratio 1mhz - 13.5mhz 0h (divide by 1) 256khz - 1mhz 1h (divide by 2) 128khz - 256khz 2h (divide by 4) 64khz - 128khz 3h (divide by 8) less than 64khz 4h (divide by 16) table 70 selection of fll_fratio in order to determine the remaining fll parameters, the fll operating frequency, f vco , must be calculated, as given by the following equation: f vco = (f out x fll_outdiv) the value of fll_n and fll_k can then be determined as follows: n.k = f vco / (fll_fratio x f ref ) see table 71 for the coding of t he fll_outdiv and fll_fratio fields. note that f ref is the input frequency, after division by fll_clk_ref_div, where applicable.
WM8904 pre-production w pp, rev 3.3, september 2012 110 in fll fractional mode, the fractional portion of the n.k multiplier is held in the fll_k register field. this field is coded as a fixed poi nt quantity, where the msb has a weighting of 0.5. note that, if desired, the value of this field may be calculated by multiplying k by 2 16 and treating fll_k as an integer value, as illustrated in the following example: if n.k = 8.192, then k = 0.192 multiplying k by 2 16 gives 0.192 x 65536 = 12582.912 (decimal) apply rounding to the nearest integer = 12583 (decimal) = 3127 (hex) for best performance, fll fractional mode should always be used. ther efore, if the calculations yield an integer value of n.k, then it is reco mmended to adjust fll_outdiv in order to obtain a non- integer value of n.k. care must always be taken to ensure that the fll operating frequency, f vco , is within its recommended limits of 90-100 mhz. the register fields that control the fll are descr ibed in table 71. example settings for a variety of reference frequencies and output frequencies are shown in table 73. register address bit label default description r116 (74h) fll control 1 2 fll_fracn_e na 0 fll fractional enable 0 = integer mode 1 = fractional mode fractional mode (fll_fracn_ena=1) is recommended in all cases 1 fll_osc_ena 0 fll oscillator enable 0 = disabled 1 = enabled fll_osc_ena must be enabled before enabling fll_ena. note that this field is required for free- running fll modes only. 0 fll_ena 0 fll enable 0 = disabled 1 = enabled fll_osc_ena must be enabled before enabling fll_ena. r117 (75h) fll control 2 13:8 fll_outdiv [5:0] 00_0000 fll fout clock divider 00_0000 = reserved 00_0001 = reserved 00_0010 = reserved 00_0011 = 4 00_0100 = 5 00_0101 = 6 ? 11_1110 = 63 11_1111 = 64 (fout = fvco / fll_outdiv)
pre-production WM8904 w pp, rev 3.3, september 2012 111 register address bit label default description 6:4 fll_ctrl_rat e [2:0] 000 frequency of the fll control block 000 = fvco / 1 (recommended value) 001 = fvco / 2 010 = fvco / 3 011 = fvco / 4 100 = fvco / 5 101 = fvco / 6 110 = fvco / 7 111 = fvco / 8 recommended that these are not changed from default. 2:0 fll_fratio [2:0] 111 f vco clock divider 000 = divide by 1 001 = divide by 2 010 = divide by 4 011 = divide by 8 1xx = divide by 16 000 recommended for f ref > 1mhz 100 recommended for f ref < 64khz r118 (76h) fll control 3 15:0 fll_k [15:0] 0000h fractional multiply for f ref (msb = 0.5) r119 (77h) fll control 4 14:5 fll_n [9:0] 177h integer multiply for f ref (lsb = 1) 3:0 fll_gain [3:0] 0h gain applied to error 0000 = x 1 (recommended value) 0001 = x 2 0010 = x 4 0011 = x 8 0100 = x 16 0101 = x 32 0110 = x 64 0111 = x 128 1000 = x 256 recommended that these are not changed from default. r120 (78h) fll control 5 4:3 fll_clk_ref_ div [1:0] 00 fll clock reference divider 00 = mclk / 1 01 = mclk / 2 10 = mclk / 4 11 = mclk / 8 mclk (or other input reference) must be divided down to <=13.5mhz. for lower power operation, the reference clock can be divided down further if desired.
WM8904 pre-production w pp, rev 3.3, september 2012 112 register address bit label default description 1:0 fll_clk_ref_ src [1:0] 00 fll clock source 00 = mclk 01 = bclk 10 = lrclk 11 = reserved table 71 fll register map free-running fll clock the fll can generate a clock signal even when no external reference is available. however, it should be noted that the accuracy of this clock is r educed, and a reference sour ce should always be used where possible. note that, in free-running mode, the fll is not sufficiently accurate for hi-fi adc or dac applications. however, the free-running mode is suitable for clocking most other functions, including the write sequencer, charge pump , dc servo and class w output driver. if an accurate reference clock is available at f ll start-up, then the fll should be configured as described above. the fll will continue to generate a st able output clock after the reference input is stopped or disconnected. if no reference clock is available at the time of st arting up the fll, then an internal clock frequency of approximately 12mhz can be generated by enabli ng the fll analogue oscillator using the fll_osc_ena register bit, and setting f out clock divider to divide by 8 (fll_outdiv = 07h), as defined in table 71. under recommended operating conditions, the fll output may be forced to approximately 12mhz by then enabling the f ll_frc_nco bit and setting fll_frc_nco_val to 19h (see table 72). the resultant sysclk deliver s the required clock frequencies for the class w output driver, dc servo, charge pump and other functions. note that the value of fll_frc_nco_val may be adjusted to control f out , but care should be taken to maintain the correct relationship between sysclk and the aforementioned functional blocks. register address bit label default description r248 (f8h) fll nco test 1 5:0 fll_frc_nco_ val [5:0] 01_1001 fll forced oscillator value valid range is 000000 to 111111 0x19h (011001) = 12mhz approx (note that this field is required for free-running fll modes only) r247 (f7h) fll nco test 0 0 fll_frc_nco 0 fll forced control select 0 = normal 1 = fll oscillator controlled by fll_frc_nco_val (note that this field is required for free-running fll modes only) table 72 fll free-running mode in both cases described above, the fll must be selected as the sysclk source by setting sysclk_src (see table 61). note that, in the absenc e of any reference clock, the fll output is subject to a very wide tolerance. see ?electrical characteristics? for details of the fll accuracy.
pre-production WM8904 w pp, rev 3.3, september 2012 113 gpio outputs from fll the WM8904 has an internal signal which indicate s whether the fll lock has been achieved. the fll lock status is an input to the interrupt contro l circuit and can be used to trigger an interrupt event - see ?interrupts?. the fll lock signal can be output directly on a gpio pin as an external indication of fll lock. see ?general purpose input/output (gpio)? for details of how to configure a gpio pin to output the fll lock signal. the fll clock can be output directly on a gpio pin as a clock signal for other circuits. note that the fll clock may be output even if the fll is not selected as the WM8904 sysclk source. the clocking configuration is illustrated in figure 59. see ?general purpose input/output (gpio)? for details of how to configure a gpio pin to output the fll clock. example fll calculation to generate 12.288 mhz output (f out ) from a 12.000 mhz reference clock (f ref ): ? set fll_clk_ref_div in order to generate f ref <=13.5mhz: fll_clk_ref_div = 00 (divide by 1) ? set fll_ctrl_rate to the recommended setting: fll_ctrl_rate = 000 (divide by 1) ? set fll_gain to the recommended setting: fll_gain = 0000 (multiply by 1) ? set fll_outdiv for the required output frequency as shown in table 69:- f out = 12.288 mhz, therefore fll_outdiv = 07h (divide by 8) ? set fll_fratio for the given refer ence frequency as shown in table 70: f ref = 12mhz, therefore fll_fratio = 0h (divide by 1) ? calculate f vco as given by f vco = f out x fll_outdiv:- f vco = 12.288 x 8 = 98.304mhz ? calculate n.k as given by n.k = f vco / (fll_fratio x f ref ): n.k = 98.304 / (1 x 12) = 8.192 ? determine fll_n and fll_k from the in teger and fractional portions of n.k:- fll_n is 8. fll_k is 0.192 ? confirm that n.k is a fractional quantity and set fll_fracn_ena: n.k is fractional. set fll_fracn_ena = 1. note that, if n.k is an integer, then an alternative value of fll_fratio should be selected in order to produce a fractional value of n.k.
WM8904 pre-production w pp, rev 3.3, september 2012 114 example fll settings table 73 provides example fll settings for generating common sysclk frequencies from a variety of low and high frequency reference inputs. f ref f out fll_clk_ ref_div f vco fll_n fll_k fll_ fratio fll_ outdiv fll_ fracn _ena 32.768 khz 12.288 mhz divide by 1 (0h) 98.304 mhz 187 (0bbh) 0.5 (8000h) 16 (4h) 8 (7h) 1 32.768 khz 11.288576 mhz divide by 1 (0h) 90.308608 mhz 344 (158h) 0.5 (8000h) 8 (3h) 8 (7h) 1 32.768 khz 11.2896 mhz divide by 1 (0h) 90.3168 mhz 344 (158h) 0.53125 (8800h) 8 (3h) 8 (7h) 1 48 khz 12.288 mhz divide by 1 (0h) 98.304 mhz 256 (100h) 0 (0000h) 8 (3h) 8 (7h) 0 12.000 mhz 12.288 mhz divide by 1 (0h) 98.3040 mhz 8 (008h) 0.192 (3127h) 1 (0h) 8 (7h) 1 12.000 mhz 11.289597 mhz divide by 1 (0h) 90.3168 mhz 7 (007h) 0.526398 (86c2h) 1 (0h) 8 (7h) 1 12.288 mhz 12.288 mhz divide by 1 (0h) 98.304 mhz 8 (008h) 0 (0000h) 1 (0h) 8 (7h) 0 12.288 mhz 11.2896 mhz divide by 1 (0h) 90.3168 mhz 7 (007h) 0.35 (599ah) 1 (0h) 8 (7h) 1 13.000 mhz 12.287990 mhz divide by 1 (0h) 98.3040 mhz 7 (007h) 0.56184 (8fd5h) 1 (0h) 8 (7h) 1 13.000 mhz 11.289606 mhz divide by 1 (0h) 90.3168 mhz 6 (006h) 0.94745 (f28ch) 1 (0h) 8 (7h) 1 19.200 mhz 12.287988 mhz divide by 2 (1h) 98.3039 mhz 5 (005h) 0.119995 (1eb8h) 1 (0h) 8 (7h) 1 19.200 mhz 11.289588 mhz divide by 2 (1h) 90.3168 mhz 4 (004h) 0.703995 (b439h) 1 (0h) 8 (7h) 1 table 73 example fll settings
pre-production WM8904 w pp, rev 3.3, september 2012 115 general purpose input/output (gpio) the WM8904 provides four multi-function pins wh ich can be configured to provide a number of different functions. these are digi tal input/output pins on the dbv dd power domain. the gpio pins are: ? irq/gpio1 ? gpio2 ? gpio3 ? bclk/gpio4 each general purpose i/o pin can be configured to be a gpio input or configured as one of a number of output functions. signal de-bounci ng can be selected on gpio input pins for use with jack/button detect applications. table 74 lists the functions that are avail able on each of the gpio pins. gpio pin function gpio pins irq / gpio1 gpio2 gpio3 bclk / gpio4 gpio input (including jack/button detect) yes yes yes yes gpio output yes yes yes yes bclk no no no yes interrupt (irq) yes yes yes yes micbias current detect yes yes yes yes micbias short-circuit detect yes yes yes yes digital microphone interface (dmic clock output) yes yes yes yes fll lock output yes yes yes yes fll clock output yes yes yes yes table 74 gpio functions available irq/gpio1 the irq/gpio1 pin is configured usi ng the register bits described in table 75. by default, this pin is irq output with pull-down resistor enabled. register address bit label default description r121 (79h) gpio control 1 5 gpio1_pu 0 gpio1 pull-up resistor enable 0 = pull-up disabled 1 = pull-up enabled 4 gpio1_pd 1 gpio1 pull-down resistor enable 0 = pull-down disabled 1 = pull-down enabled 3:0 gpio1_sel [3:0] 0100 gpio1 function select 0000 = input pin 0001 = clock output (f=sysclk/opclkdiv) 0010 = logic '0' 0011 = logic '1' 0100 = irq (default) 0101 = fll lock 0110 = mic detect 0111 = mic short 1000 = dmic clock out 1001 = fll clock output 1010 to 1111 = reserved table 75 irq/gpio1 control
WM8904 pre-production w pp, rev 3.3, september 2012 116 gpio2 the gpio2 pin is configured using t he register bits described in table 76. by default, this pin is gpio input with pull-down resistor enabled. register address bit label default description r122 (7ah) gpio control 2 5 gpio2_pu 0 gpio2 pull-up resistor enable 0 = pull-up disabled 1 = pull-up enabled 4 gpio2_pd 1 gpio2 pull-down resistor enable 0 = pull-down disabled 1 = pull-down enabled 3:0 gpio2_sel [3:0] 0000 gpio2 function select 0000 = input pin (default) 0001 = clock output (f=sysclk/opclkdiv) 0010 = logic '0' 0011 = logic '1' 0100 = irq 0101 = fll lock 0110 = mic detect 0111 = mic short 1000 = dmic clock out 1001 = fll clock output 1010 to 1111 = reserved table 76 gpio2 control gpio3 the gpio3 pin is configured using t he register bits described in table 77. by default, this pin is gpio input with pull-down resistor enabled. register address bit label default description r123 (7bh) gpio control 3 5 gpio3_pu 0 gpio3 pull-up resistor enable 0 = pull-up disabled 1 = pull-up enabled 4 gpio3_pd 1 gpio3 pull-down resistor enable 0 = pull-down disabled 1 = pull-down enabled 3:0 gpio3_sel [3:0] 0000 gpio3 function select 0000 = input pin (default) 0001 = clock output (f=sysclk/opclkdiv) 0010 = logic '0' 0011 = logic '1' 0100 = irq 0101 = fll lock 0110 = mic detect 0111 = mic short 1000 = dmic clock out 1001 = fll clock output 1010 to 1111 = reserved table 77 gpio3 control
pre-production WM8904 w pp, rev 3.3, september 2012 117 bclk/gpio4 the bclk/gpio4 pin is configured using the register bits described in table 78. by default, this pin provides the bclk function associated with the digital audio interface. the bclk function can operate in slave mode (bclk input) or in master mode (bclk output), depending on the bclk_dir register bit as described in the ?d igital audio interface? section. it is possible to configure the bclk/gpio4 pin to provide various gpio func tions; in this case, the bclk function is provided using the mclk pin. note that the bclk function is always in slave mode (bclk input) in this mode. to select the gpio4 functions, it is required to set bclk_dir = 0 (see table 56) and to set gpio_bclk_mode_ena = 1 (see table 78 below). in th is configuration, the mclk input is used as the bit-clock (bclk) for the digital audio interface. when the bclk/gpio4 pin is c onfigured as gpio4, then the pi n function is determined by the gpio_bclk_sel register field. register address bit label default description r124 (7ch) gpio control 4 7 gpio_bclk_mode_ ena 0 selects bclk/gpio4 pin function 0 = bclk/gpio4 is used as bclk 1 = bclk/gpio4 is used as gpio. mclk provides the bclk in the aif in this mode. 3:0 gpio_bclk_sel [3:0] 0000 gpio_bclk function select: 0000 = input pin (default) 0001 = clock output (f=sysclk/opclkdiv) 0010 = logic '0' 0011 = logic '1' 0100 = irq 0101 = fll lock 0110 = mic detect 0111 = mic short 1000 = dmic clock out 1001 = fll clock output 1010 to 1111 = reserved table 78 bclk/gpio4 control
WM8904 pre-production w pp, rev 3.3, september 2012 118 interrupts the interrupt controller has multiple inputs; t hese include the gpio input pins and the micbias current detection circuits. any comb ination of these inputs can be us ed to trigger an interrupt (irq) event. WM8904 interrupt events may be triggered in response to external gpio inputs, fll lock status, micbias status or write sequencer status. note t hat the gpio inputs (inc luding gpi7 and gpi8) are only supported as interrupt events when the res pective pin is confi gured as a gpio input. there is an interrupt status field associated with each of the irq inputs. these are contained in the interrupt status register (r127), as described in table 79. the status of the irq inputs can be read from this register at any time, or in response to the interrupt output being signalled via a gpio pin. individual mask bits can select or deselect different functions from t he interrupt controller. these are listed within the interrupt status mask register (r128), as described in table 80. note that the interrupt status fields remain valid, even when masked, but the masked bits will not cause the interrupt (irq) output to be asserted. the interrupt (irq) output represents the logical ?or? of all unmasked irq inputs. the bits within the interrupt status register (r127) ar e latching fields and, once set, are not reset until a ?1? is written to the respective register bit in the interrupt status register. the interrupt (irq) output is not reset until each of the unmasked irq inputs has been reset. each of the irq inputs can be individually inverted in the interrupt function, enabling either active high or active low behaviour on eac h irq input. the polarity inversi on is controlled using the bits contained in the interrupt polarity register (r129). each of the irq inputs can be debounced to ensure that spikes and transient glitches do not assert the interrupt output. this is selected using the bits contained in the interrupt debounce register (r130). the WM8904 interrupt controller circuit is illustrated in figure 60. the associated control fields are described in table 79 through to table 82. figure 60 interrupt controller
pre-production WM8904 w pp, rev 3.3, september 2012 119 register address bit label default description r127 (7fh) interrupt status 10 irq 0 logical or of all other interrupt flags 9 gpio_bclk_eint 0 gpio4 interrupt 0 = interrupt not set 1 = interrupt is set cleared when a ?1? is written 8 wseq_eint 0 write sequence interrupt 0 = interrupt not set 1 = interrupt is set cleared when a ?1? is written. note that the read value of wseq_eint is not valid whilst the write sequencer is busy 7 gpio3_eint 0 gpio3 interrupt 0 = interrupt not set 1 = interrupt is set cleared when a ?1? is written 6 gpio2_eint 0 gpio2 interrupt 0 = interrupt not set 1 = interrupt is set cleared when a ?1? is written 5 gpio1_eint 0 gpio1 interrupt 0 = interrupt not set 1 = interrupt is set cleared when a ?1? is written 4 gpi8_eint 0 gpi8 interrupt 0 = interrupt not set 1 = interrupt is set cleared when a ?1? is written 3 gpi7_eint 0 gpi7 interrupt 0 = interrupt not set 1 = interrupt is set cleared when a ?1? is written 2 fll_lock_eint 0 fll lock interrupt 0 = interrupt not set 1 = interrupt is set cleared when a ?1? is written 1 mic_shrt_eint 0 micbias short circuit interrupt 0 = interrupt not set 1 = interrupt is set cleared when a ?1? is written 0 mic_det_eint 0 micbias current detect interrupt 0 = interrupt not set 1 = interrupt is set cleared when a ?1? is written table 79 interrupt status registers
WM8904 pre-production w pp, rev 3.3, september 2012 120 register address bit label default description r128 (80h) interrupt status mask 9 im_gpio_bclk_eint 1 gpio4 interrupt mask 0 = do not mask interrupt 1 = mask interrupt 8 im_wseq_eint 1 write sequencer interrupt mask 0 = do not mask interrupt 1 = mask interrupt 7 im_gpio3_eint 1 gpio3 interrupt mask 0 = do not mask interrupt 1 = mask interrupt 6 im_gpio2_eint 1 gpio2 interrupt mask 0 = do not mask interrupt 1 = mask interrupt 5 im_gpio1_eint 1 gpio1 interrupt mask 0 = do not mask interrupt 1 = mask interrupt 4 im_gpi8_eint 1 gpi8 interrupt mask 0 = do not mask interrupt 1 = mask interrupt 3 im_gpi7_eint 1 gpi7 interrupt mask 0 = do not mask interrupt 1 = mask interrupt 2 im_fll_lock_eint 1 fll lock interrupt mask 0 = do not mask interrupt 1 = mask interrupt 1 im_mic_shrt_eint 1 micbias short circuit interrupt mask 0 = do not mask interrupt 1 = mask interrupt 0 im_mic_det_eint 1 micbias current detect interrupt mask 0 = do not mask interrupt 1 = mask interrupt table 80 interrupt mask registers register address bit label default description r129 (81h) interrupt polarity 9 gpio_bclk_eint_pol 0 gpio4 interrupt polarity 0 = active high 1 = active low 8 wseq_eint_pol 0 write sequencer interrupt polarity 0 = active high (interrupt is triggered when wseq is busy) 1 = active low (interrupt is triggered when wseq is idle) 7 gpio3_eint_pol 0 gpio3 interrupt polarity 0 = active high 1 = active low
pre-production WM8904 w pp, rev 3.3, september 2012 121 register address bit label default description 6 gpio2_eint_pol 0 gpio2 interrupt polarity 0 = active high 1 = active low 5 gpio1_eint_pol 0 gpio1 interrupt polarity 0 = active high 1 = active low 4 gpi8_eint_pol 0 gpi8 interrupt polarity 0 = active high 1 = active low 3 gpi7_eint_pol 0 gpi7 interrupt polarity 0 = active high 1 = active low 2 fll_lock_eint_pol 0 fll lock interrupt polarity 0 = active high (interrupt is triggered when fll lock is reached) 1 = active low (interrupt is triggered when fll is not locked) 1 mic_shrt_eint_pol 0 micbias short circuit interrupt polarity 0 = active high 1 = active low 0 mic_det_eint_pol 0 micbias current detect interrupt polarity 0 = active high 1 = active low table 81 interrupt polarity registers register address bit label default description r130 (82h) interrupt debounce 9 gpio_bclk_eint_db 0 gpio4 interrupt debounce 0 = disabled 1 = enabled 8 wseq_eint_db 0 write sequencer interrupt debounce enable 0 = disabled 1 = enabled 7 gpio3_eint_db 0 gpio3 input debounce 0 = disabled 1 = enabled 6 gpio2_eint_db 0 gpio2 input debounce 0 = disabled 1 = enabled 5 gpio1_eint_db 0 gpio1 input debounce 0 = disabled 1 = enabled 4 gpi8_eint_db 0 gpi8 input debounce 0 = disabled 1 = enabled
WM8904 pre-production w pp, rev 3.3, september 2012 122 register address bit label default description 3 gpi7_eint_db 0 gpi7 input debounce 0 = disabled 1 = enabled 2 fll_lock_eint_db 0 fll lock debounce 0 = disabled 1 = enabled 1 mic_shrt_eint_db 0 micbias short circuit interrupt debounce 0 = disabled 1 = enabled 0 mic_det_eint_db 0 micbias current detect interrupt debounce 0 = disabled 1 = enabled table 82 interrupt debounce registers using in1l and in1r as interrupt inputs in1l pin has three input functions. ? analogue audio input ? digital microphone input (dmicdat1) ? digital interrupt input (gpi7) in1r pin has three input functions. ? analogue audio input ? digital microphone input (dmicdat2) ? digital interrupt input (gpi8) to use these pins as digita l interrupt inputs, they must be enabled using the gpi7_ena and gpi8_ena bits as described in table 83. register address bit label default description r124 (7ch) gpio control 4 9 gpi7_ena 0 gpi7 input enable 0 = disabled 1 = enabled 8 gpi8_ena 0 gpi8 input enable 0 = disabled 1 = enabled table 83 enabling in1l and in1r as interrupts gpi7 and gpi8
pre-production WM8904 w pp, rev 3.3, september 2012 123 control interface the WM8904 is controlled by writing to registers thr ough a 2-wire serial control interface. readback is available for all registers, including chip id, power management status and gpio status. note that, if it cannot be assured that mclk is pr esent when accessing the register map, then it is required to set clk_sys_ena = 0 to ensure correct operation. see ?clocking and sample rates? for details of clk_sys_ena. the WM8904 is a slave device on the control interfac e; sclk is a clock input, while sda is a bi- directional data pin. to allow arbitration of multip le slaves (and/or multip le masters) on the same interface, the WM8904 transmits logic 1 by tri-stat ing the sda pin, rather than pulling it high. an external pull-up resistor is requir ed to pull the sda line high so that the logic 1 can be recognised by the master. in order to allow many devices to share a singl e 2-wire control bus, ever y device on the bus has a unique 8-bit device id (this is not the same as t he 8-bit address of each register in the WM8904). the WM8904 device id is 0011 0100 (34h). the lsb of the devic e id is the read/write bit; this bit is set to logic 1 for ?read? and logic 0 for ?write?. the WM8904 operates as a slave device only. the controller indicates the start of data transfer with a high to low transition on sda while sclk remains hi gh. this indicates that a device id, register address and data will follow. the WM8904 responds to t he start condition and shifts in the next eight bits on sda (8-bit device id including read/write bit, msb first). if the dev ice id received matches the device id of the WM8904, then the WM8904 responds by pulling sda low on the next clock pulse (ack). if the device id is not re cognised or the r/w bit is ?1? when operating in write only mode, the WM8904 returns to the idle condition and waits for a new start condition and valid address. if the device id matches the device id of the WM8904, the data transfer continues as described below. the controller indicates the end of data trans fer with a low to high transition on sda while sclk remains high. after receiving a complete address and data sequence the WM8904 returns to the idle state and waits for another start condition. if a start or stop condition is detected out of sequence at any point during data transfer (i.e. sda changes while sclk is high), the device returns to the idle condition. the WM8904 supports the following read and write operations: ? single write ? single read ? multiple write using auto-increment ? multiple read using auto-increment the sequence of signals associated with a single regi ster write operation is illustrated in figure 61. figure 61 control interface register write the sequence of signals associated with a single regi ster read operation is illustrated in figure 62.
WM8904 pre-production w pp, rev 3.3, september 2012 124 figure 62 control interface register read the control interface also supports other register operations, as listed above. the interface protocol for these operations is summarised below. the terminology used in the following figures is detailed in table 84. note that multiple write and multiple read operat ions are supported using the auto-increment mode. this feature enables the host processor to access sequential blocks of the data in the WM8904 register map faster than is possibl e with single register operations. terminology description s start condition sr repeated start a acknowledge (sda low) a not acknowledge (sda high) p stop condition r/w readnotwrite 0 = write 1 = read [white field] data flow from bus master to WM8904 [grey field] data flow from WM8904 to bus master table 84 control interface terminology figure 63 single register write to specified address figure 64 single register read from specified address figure 65 multiple register write to specified address using auto-increment
pre-production WM8904 w pp, rev 3.3, september 2012 125 sr s a register address (0) a a (1) read from 'register address' msbyte data 0 lsbyte data 0 a a p msbyte data n lsbyte data n a a a msbyte data n-1 lsbyte data n-1 a a read from 'last register address+n' read from 'last register address+n-1' device id rw device id rw figure 66 multiple register read from specified address using auto-increment figure 67 multiple register read from last address using auto-increment control write sequencer the control write sequencer is a programmable unit that forms part of the WM8904 control interface logic. it provides the ability to perform a sequence of register write operations with the minimum of demands on the host processor - the sequence may be initiated by a single operation from the host processor and then left to execute independently. default sequences for start-up and shutdown are provided (see ?default s equences? section). it is recommended that these default sequences ar e used unless changes become necessary. when a sequence is initiated, the sequencer performs a series of pre-defined register writes. the host processor informs the sequencer of the st art index of the required sequence within the sequencer?s memory. at each step of the sequence, t he contents of the selected register fields are read from the sequencer?s memory and copied into the WM8904 control registers. this continues sequentially through the sequencer?s memory until an ?end of sequence? bit is encountered; at this point, the sequencer stops and an interrupt status flag is asserted. for cases where the timing of the write sequence is important, a programmable delay c an be set for specific steps within the sequence. note that the control write sequencer?s internal cl ock is derived from the internal clock sysclk. an external mclk signal must be present when usi ng the control write sequencer, and sysclk must be enabled by setting clk_sys_ena (see ?clocking and sample rates?). the clock division from mclk is handled transparently by the WM8904 without user intervention, as long as mclk and sample rates are set correctly. initiating a sequence the register fields associated with running the control write sequencer are described in table 85. the write sequencer clock is enabled by setting the wseq_ena bit. note that the operation of the control write sequencer also requires the in ternal clock sysclk to be enabled via the clk_sys_ena (see ?clocking and sample rates?). the start index of the required sequence must be written to the wseq_start_index field. setting the wseq_start bit initiates the sequencer at the given start index.
WM8904 pre-production w pp, rev 3.3, september 2012 126 the write sequencer can be interrupted by wr iting a logic 1 to the wseq_abort bit. the current status of the write sequencer can be r ead using two further register fields - when the wseq_busy bit is asserted, this indicates that the write sequencer is busy. note that, whilst the control write sequencer is running a sequence (indicated by the wseq_busy bit), normal read/write operations to the control registers cannot be supported. (the write sequencer registers and the software reset register can still be access ed when the sequencer is busy.) the index of the current step in the write sequencer can be read fr om the wseq_current_index field; this is an indicator of the sequencer?s progress. on completion of a sequence, this field holds the index of the last step within the last commanded sequence. when the write sequencer reaches the end of a sequence, it asserts the wseq_eint flag in register r127 (see table 79 within the ?interrupt s? section). this flag can be used to generate an interrupt event on completion of the sequence. note that the wseq_eint flag is asserted to indicate that the wseq is not busy. register address bit label default description r108 (6ch) write sequencer 0 8 wseq_ena 0 write sequencer enable. 0 = disabled 1 = enabled r111 (6fh) write sequencer 3 9 wseq_abort 0 writing a 1 to this bit aborts the current sequence and returns control of the device back to the serial control interface. 8 wseq_start 0 writing a 1 to this bit starts the write sequencer at the memory location indicated by the wseq_start_index field. the sequence continues until it reaches an ?end of sequence? flag. at the end of the sequence, this bit will be reset by the write sequencer. 5:0 wseq_start_ index [5:0] 00_0000 sequence start index. this is the memory location of the first command in the selected sequence. 0 to 31 = ram addresses 32 to 48 = rom addresses 49 to 63 = reserved r112 (70h) write sequencer 4 9:4 wseq_curre nt_index [5:0] 00_0000 sequence current index (read only): this is the location of the most recently accessed command in the write sequencer memory. 0 wseq_busy 0 sequencer busy flag (read only): 0 = sequencer idle 1 = sequencer busy note: it is not possible to write to control registers via the control interface while the sequencer is busy. table 85 write sequencer control - initiating a sequence programming a sequence a sequence consists of write operations to data bits (or groups of bits ) within the control registers. the register fields associated with programming the control write sequencer are described in table 86. for each step of the sequence being programmed, the sequencer index must be written to the wseq_write_index field. the values 0 to 31 correspond to all the available ram addresses within the write sequencer memory. (note that memory addresses 32 to 48 also exist, but these are rom addresses, which are not programmable.)
pre-production WM8904 w pp, rev 3.3, september 2012 127 having set the index as described above, register r109 must be written to (containing the control register address, the start bit position and the fi eld width applicable to this step of the sequence). also, register r110 must be written to (containi ng the register data, the end of sequence flag and the delay time required after this step is executed). after writing to these two registers, the next step in the sequence may be programmed by updat ing wseq_write_index and repeating the procedure. wseq_addr is an 8-bit field contai ning the control register address in which the data should be written. wseq_data_start is a 4-bit field which identifie s the lsb position within the selected control register to which the data should be written. setting wseq_data_start = 0100 will cause 1-bit data to be written to bit 4. with this setting, 4-bit data would be written to bits 7:4 and so on. wseq_data_width is a 3-bit field which identifies the width of the data block to be written. this enables selected portions of a control register to be updated without any concern for other bits within the same register, eliminating the need for read-modi fy-write procedures. values of 0 to 7 correspond to data widths of 1 to 8 respectively. for ex ample, setting wseq_data_width = 010 will cause a 3-bit data block to be written. note that the maxi mum value of this field corresponds to an 8-bit data block; writing to register fields greater t han 8 bits wide must be performed using two separate operations of the control write sequencer. wseq_data is an 8-bit field which contains the data to be written to the selected control register. the wseq_data_width field determines how many of these bits are written to the selected register; the most significant bi ts (above the number indicated by wseq_data_width) are ignored. wseq_delay is a 4-bit field which controls t he waiting time between the current step and the next step in the sequence. the total delay time per step (including execut ion) is given by: t = k (2 wseq_delay + 8) where k = 62.5 ? s (under recommended operating conditions) this gives a useful range of execution/delay times from 562 ? s up to 2.048s per step. wseq_eos is a 1-bit field which indicates the end of sequence. if this bit is set, then the control write sequencer will automatically stop after this step has been executed. register address bit label default description r108 (6ch) write sequencer 0 4:0 wseq_write _index [4:0] 0_0000 sequence write index. this is the memory location to which any updates to r109 and r110 will be copied. 0 to 31 = ram addresses r109 (6dh) write sequencer 1 14:12 wseq_data_ width [2:0] 000 width of the data block written in this sequence step. 000 = 1 bit 001 = 2 bits 010 = 3 bits 011 = 4 bits 100 = 5 bits 101 = 6 bits 110 = 7 bits 111 = 8 bits 11:8 wseq_data_ start [3:0] 0000 bit position of the lsb of the data block written in this sequence step. 0000 = bit 0 ? 1111 = bit 15 7:0 wseq_addr [7:0] 0000_0000 control register address to be written to in this sequence step.
WM8904 pre-production w pp, rev 3.3, september 2012 128 register address bit label default description r110 (6eh) write sequencer 2 14 wseq_eos 0 end of sequence flag. this bit indicates whether the control write sequencer should stop after executing this step. 0 = not end of sequence 1 = end of sequence (stop the sequencer after this step). 11:8 wseq_delay [3:0] 0000 time delay after executing this step. total delay time per step (including execution)= 62.5s (2^wseq_delay + 8) 7:0 wseq_data [7:0] 0000_0000 data to be written in this sequence step. when the data width is less than 8 bits, then one or more of the msbs of wseq_data are ignored. it is recommended that unused bits be set to 0. table 86 write sequencer control - programming a sequence note that a ?dummy? write can be inserted into a control sequence by commanding the sequencer to write a value of 0 to bit 0 of register r255 (ffh). th is is effectively a write to a non-existent register location. this can be used in order to create pl aceholders ready for easy adaptation of the sequence. for example, a sequence could be defined to power-up a mono signal path from dacl to headphone, with a ?dummy? write included to leave spac e for easy modification to a stereo signal path configuration. dummy writes can also be used in order to implement additional time delays between register writes. dummy writes are included in the default start-up sequence ? see table 88. in summary, the control register to be written is set by the wseq_addr field. the data bits that are written are determined by a combination of wseq_data_start, wseq_data_width and wseq_data. this is illustrated below for an example case of writing to the vmid_res field within register r5 (05h). in this example, the start position is bit 01 (wseq_data_start = 0001b) and the data width is 2 bits (wseq_data_width = 0001b). with these settings, the control write sequencer would updated the control register r5 [2:1] with the contents of wseq_data [1:0]. b15 b14 b13 b12 b11 b10 b09 b08 b07 b06 b05 b04 b03 b02 b01 b00 r5 (05h) vmid control 0 lsb position = b01 wseq_data_start n = 0001 data width = 2 bits wseq_data_width n = 0001 wseq_data n (8 bits) b07 b06 b05 b04 b03 b02 b01 b00 wseq_data_width n = 2 bits. therefore, only the least significant 2 bits are valid. bits 02 to 07 are discarded vmid_res figure 68 control write sequencer example
pre-production WM8904 w pp, rev 3.3, september 2012 129 default sequences when the WM8904 is powered up, two control wr ite sequences are available through default settings in both ram and rom memory locations. the purpose of these sequences, and the register write required to initiate them, is summarised in t able 87. in both cases, a single register write will initiate the sequence. wseq start index wseq finish index purpose to initiate 0 (00h) 22 (16h) start-up sequence write 0100h to register r111 (6fh) 25 (19h) 39 (27h) shutdown sequence write 0119h to register r111 (6fh) table 87 write sequencer default sequences note on shutdown sequence: the instruction at index address 25 (19h) shorts the outputs lineoutl and lineoutr. if the line outputs are not in use at the time the sequence is run, then the sequence could, instead, be started at index address 26. index addresses 0 to 31 may be programmed to user s? own settings at any time, as described in ?programming a sequence?. users? ow n settings remain in memory and are not affected by software resets (i.e. writing to register r0). however, any non-default sequences are lost when the device is powered down. start-up sequence the start-up sequence is initiated by writing 0100h to register r111 (6fh). this single operation starts the control write sequencer at index addr ess 0 (00h) and executes the sequence defined in table 88. for typical clocking configurations with mclk =12.288mhz, this sequence takes approximately 300ms to run. note that, for fast startup, step 18 may be overwritten with dummy data in order to achieve startup within 50ms (see ?quick start-up and shutdown?). wseq index register address width start data delay eos description 0 (00h) r4 (04h) 5 bits bit 0 1ah 0h 0b isel = 10b bias_ena = 0 (delay = 0.5625ms) 1 (01h) r5 (05h) 8 bits bit 0 47h 6h 0b vmid_buf_ena = 1 vmid_res[1:0] = 11b vmid_ena = 1 (delay = 4.5ms) 2 (02h) r5 (05h) 2 bits bit 1 01h 0h 0b vmid_res[1:0] = 01b (delay = 0.5625ms) 3 (03h) r4 (04h) 1 bit bit 0 01h 0h 0b bias_ena = 1 (delay = 0.5625ms) 4 (04h) r14 (0eh) 2 bits bit 0 03h 0h 0b hpl_pga_ena = 1 hpr_pga_ena = 1 (delay = 0.5625ms) 5 (05h) r15 (0fh) 2 bits bit 0 03h 0h 0b lineoutl_pga_ena = 1 lineoutr_pga_ena = 1 (delay = 0.5625ms) 6 (06h) r22 (16h) 1 bit bit 1 01h 0h 0b clk_dsp_ena = 1 (delay = 0.5625ms)
WM8904 pre-production w pp, rev 3.3, september 2012 130 wseq index register address width start data delay eos description 7 (07h) r18 (12h) 2 bits bit 2 03h 5h 0b dacl_ena = 1 dacr_ena = 1 (delay = 2.5ms) 8 (08h) r255 (ffh) 1 bit bit 0 00h 0h 0b dummy write for expansion (delay = 0.5625ms) 9 (09h) r4 (04h) 1 bit bit 4 00h 0h 0b (delay = 0.5625ms) 10 (0ah) r98 (62h) 1 bit bit 0 01h 6h 0b cp_ena = 1 (delay = 4.5ms) 11 (0bh) r255 (ffh) 1 bit bit 0 00h 0h 0b dummy write for expansion (delay = 0.5625ms) 12 (0ch) r90 (5ah) 8 bits bit 0 11h 0h 0b hpl_ena = 1 hpr_ena = 1 (delay = 0.5625ms) 13 (0dh) r94 (5eh) 8 bits bit 0 11h 0h 0b lineoutl_ena = 1 lineoutr_ena = 1 (delay = 0.5625ms) 14 (0eh) r90 (5ah) 8 bits bit 0 33h 0h 0b hpl_ena_dly = 1 hpr_ena_dly = 1 (delay = 0.5625ms) 15 (0fh) r94 (5eh) 8 bits bit 0 33h 0h 0b lineoutl_ena_dly = 1 lineoutr_ena_dly = 1 (delay = 0.5625ms) 16 (10h) r67 (43h) 4 bits bit 0 0fh ch 0b dcs_ena_chan_0 = 1 dcs_ena_chan_1 = 1 dcs_ena_chan_2 = 1 dcs_ena_chan_3 = 1 (delay = 0.5625ms) 17 (11h) r68 (44h) 8 bits bit 0 f0h 0h 0b dcs_trig_startup_0 = 1 dcs_trig_startup_1 = 1 dcs_trig_startup_2 = 1 dcs_trig_startup_3 = 1 (delay = 256.5ms) 18 (12h) r255 (ffh) 1 bit bit 0 00h 0h 0b dummy write for expansion (delay = 0.5625ms) 19 (13h) r90 (5ah) 8 bits bit 0 77h 0h 0b hpl_ena_outp = 1 hpr_ena_outp = 1 (delay = 0.5625ms) 20 (14h) r94 (5eh) 8 bits bit 0 77h 0h 0b lineoutl_ena_outp = 1 lineoutr_ena_outp = 1 (delay = 0.5625ms) 21 (15h) r90 (5ah) 8 bits bit 0 ffh 0h 0b hpl_rmv_short = 1 hpr_rmv_short = 1 (delay = 0.5625ms) 22 (16h) r94 (5eh) 8 bits bit 0 ffh 0h 1b lineoutl_rmv_short = 1 lineoutr_rmv_short = 1 end of sequence 23 (17h) r255 (ffh) 1 bit bit 0 00h 0h 0b spare 24 (18h) r255 (ffh) 1 bit bit 0 00h 0h 0b spare table 88 start-up sequence
pre-production WM8904 w pp, rev 3.3, september 2012 131 shutdown sequence the shutdown sequence is initiated by writing 0119h to register r111 (6fh). this single operation starts the control write sequencer at index a ddress 25 (19h) and executes the sequence defined in table 89. for typical clocking configurations with mclk =12.288mhz, this sequence takes approximately 350ms to run. wseq index register address width start data delay eos description 25 (19h) r94 (5eh) 8 bits bit 0 77h 0h 0b lineoutl_rmv_short = 0 lineoutr_rmv_short = 0 (delay = 0.5625ms) 26 (1ah) r90 (5ah) 8 bits bit 0 77h 0h 0b hpl_rmv_short = 0 hpr_rmv_short = 0 (delay = 0.5625ms) 27 (1bh) r90 (5ah) 8 bits bit 0 00h 0h 0b hpl_ena_outp = 0 hpl_ena_dly = 0 hpl_ena = 0 hpr_ena_outp = 0 hpr_ena_dly = 0 hpr_ena = 0 (delay = 0.5625ms) 28 (1ch) r94 (5eh) 8 bits bit 0 00h 0h 0b lineoutl_ena_outp = 0 lineoutl_ena_dly = 0 lineoutl_ena = 0 lineoutr_ena_outp = 0 lineoutr_ena_dly = 0 lineoutr_ena = 0 (delay = 0.5625ms) 29 (1dh) r67 (43h) 4 bits bit 0 00h 0h 0b dcs_ena_chan_0 = 0 dcs_ena_chan_1 = 0 dcs_ena_chan_2 = 0 dcs_ena_chan_3 = 0 (delay = 0.5625ms) 30 (1eh) r98 (62h) 1 bit bit 0 00h 0h 0b cp_ena = 0 (delay = 0.5625ms) 31 (1fh) r18 (12h) 2 bits bit 2 00h 0h 0b dacl_ena = 0 dacr_ena = 0 (delay = 0.5625ms) 32 (20h) r22 (16h) 1 bit bit 1 00h 0h 0b clk_dsp_ena = 0 (delay = 0.5625ms) 33 (21h) r14 (0eh) 2 bits bit 0 00h 0h 0b hpl_pga_ena = 0 hpr_pga_ena = 0 (delay = 0.5625ms) 34 (22h) r15 (0fh) 2 bits bit 0 00h 0h 0b lineoutl_pga_ena = 0 lineoutr_pga_ena = 0 (delay = 0.5625ms) 35 (23h) r4 (04h) 1 bit bit 0 00h 0h 0b bias_ena = 0 (delay = 0.5625ms) 36 (24h) r5 (05h) 1 bit bit 0 00h ch 0b vmid_ena = 0 (delay = 256.5ms) 37 (25h) r5 (05h) 1 bit bit 0 00h 9h 0b vmid_ena = 0 (delay = 32.5ms) 38 (26h) r5 (05h) 8 bits bit 0 00h 0h 0b vmid_buf_ena = 0
WM8904 pre-production w pp, rev 3.3, september 2012 132 wseq index register address width start data delay eos description vmid_res[1:0] = 00 vmid_ena = 0 (delay = 0.5625ms) 39 (27h) r4 (04h) 2 bits bit 0 00h 0h 1b bias_ena = 0 end of sequence table 89 shutdown sequence
pre-production WM8904 w pp, rev 3.3, september 2012 133 power-on reset the WM8904 includes an internal power-on-reset (por ) circuit, which is used to reset the digital logic into a default state after power up. the por circuit is powered from avdd and monitors dcvdd. the internal por signal is asserted low when avdd or dcvdd are below minimum thresholds. the specific behaviour of the circuit will vary, depending on the relative timing of the supply voltages. typical scenarios are illustrated in figure 69 and figure 70. dcvdd v pord_on 0v avdd 0v v pora v pora_off lo hi internal por device ready por active por active por undefined figure 69 power on reset timing - avdd enabled first dcvdd 0v avdd 0v v pora v pord_off lo hi internal por device ready v pora_on por active por active por undefined figure 70 power on reset timing - dcvdd enabled first
WM8904 pre-production w pp, rev 3.3, september 2012 134 the por signal is undefined until avdd has exceeded the minimum threshold, v pora once this threshold has been exceeded, por is asserted low and the chip is held in reset. in this condition, all writes to the control interface are ignored. once avdd and dcvdd have r eached their respective power on thresholds, por is released high, all registers are in their default state, and writes to the control interface may take place. note that a minimum power-on reset period, t por , applies even if avdd and dcvdd have zero rise time. (this specification is guarant eed by design rather than test.) on power down, por is asserted low when any of avdd or dcvdd falls below their respective power-down thresholds. typical power-on reset parameters for the WM8904 are defined in table 90. symbol description typ unit v pora avdd threshold below which por is undefined 0.25 v v pora_on power-on threshold (avdd) 1.15 v v pora_off power-off threshold (avdd) 1.12 v v pord_on power-on threshold (dcvdd) 0.57 v v pord_off power-off threshold (dcvdd) 0.55 v t por minimum power-on reset period 9.5 ? s table 90 typical power-on reset parameters notes: 1. if avdd and dcvdd suffer a brown-out (i.e. drop below the minimum recommended operating level but do not go below v pora_off or v pord_off ) then the chip does not reset and resumes normal operation when the voltage is back to the recommended level again. 2. the chip enters reset at power down when avdd or dcvdd falls below v pora_off or v pord_off . this may be important if the supply is turned on and off frequently by a power management system. 3. the minimum t por period is maintained even if dcvdd and avdd have zero rise time. this specification is guaranteed by design rather than test.
pre-production WM8904 w pp, rev 3.3, september 2012 135 quick start-up and shutdown the WM8904 has the capability to perform a quick st art-up and shutdown with a minimum number of register operations. this is ac hieved using the control write s equencer, which is configured with default start-up settings that set up the dev ice for dac playback via headphone and line output. assuming a 12.288mhz external clock, the star t-up sequence configures the device for 48khz playback mode. the default start-up sequence requires three regi ster write operations. the default shutdown sequence requires just a single register write. t he minimum procedure for executing the quick start- up and shutdown sequences is descr ibed below. see ?control write sequencer? for more details. after the default start-up sequence has been performed, the dc offset correction values will be held in memory, provided that power is maintained and a software reset is not performed. fast start-up using the stored values of dc offset correct ion is also possible, as described below. quick start-up (default sequence) an external clock must be applied to mclk. assu ming 12.288mhz input clock, the start-up sequence will take approximately 300ms to complete. the following register operations will initiate the quick start-up sequence. register address value description r108 (6ch) write sequencer 0 0100h wseq_ena = 1 wseq_write_index = 00h this enables the write sequencer r111 (6fh) write sequencer 3 0100h wseq_abort = 0 wseq_start = 1 wseq_start_index = 00h this starts the write sequenc er at index address 0 (00h) r33 (21h) dac digital 1 0000h dac_mono = 0 dac_sb_filt = 0 dac_muterate = 0 dac_unmute_ramp = 0 dac_osr128 = 0 dac_mute = 0 deemph = 00 this un-mutes the dacs table 91 quick start-up control the wseq_busy bit (in register r112, see tabl e 85) will be set to 1 while the sequence runs. when this bit returns to 0, the device has been set up and is ready for dac playback operation. fast start-up from standby the default start-up sequence runs the dc servo to re move dc offsets from the outputs. the offset for this path selection is then stored in memory. pr ovided that power is maintained to the chip, and a software reset is not performed, then the dc offset correction will be held in memory on the WM8904. this allows the dc servo calibrations to be omitted from the start-up sequence if the offset correction has already been performed. by omitting this part of the start-up sequence, a fast start-up time of less than 50ms can be achieved. the register write sequence described in table 92 replaces the default dc servo operation with dummy operations, allowing a fast start-up to be ac hieved, assuming the device is initially in a standby condition with dc offset co rrection previously performed.
WM8904 pre-production w pp, rev 3.3, september 2012 136 note that, if power is removed from the WM8904 or if a software reset is performed, then the default sequence will be restored, and the dc offset correct ion will be necessary on the output paths once more. register address value description r108 (6ch) write sequencer 0 0111h wseq_ena = 1 wseq_write_index = 11h this enables the write sequencer and selects wseq index 17 (11h) for modification r109 (6dh) write sequencer 1 00ffh wseq_data_width = 000 wseq_data_start = 0000 wseq_addr = ffh this modifies wseq index 17 (11h) with dummy step r110 (6eh) write sequencer 2 0000h wseq_eos = 0 wseq_delay = 0000 wseq_data = 00h this modifies wseq index 17 (11h) with dummy step r111 (6fh) write sequencer 3 0100h wseq_abort = 0 wseq_start = 1 wseq_start_index = 00h this starts the write sequenc er at index address 0 (00h) r33 (21h) dac digital 1 0000h dac_mono = 0 dac_sb_filt = 0 dac_muterate = 0 dac_unmute_ramp = 0 dac_osr128 = 0 dac_mute = 0 deemph = 00 this un-mutes the dacs table 92 fast start-up from standby control the wseq_busy bit (in register r112, see tabl e 85) will be set to 1 while the sequence runs. when this bit returns to 0, the device has been set up and is ready for dac playback operation. quick shutdown (default sequence) the default shutdown sequence assumes the initial dev ice conditions are as c onfigured by the default start-up sequence. assuming 12.288mhz input clock, the shutdown sequence will take approximately 350ms to complete. the following register operation will initiate the default shutdown sequence. register address value description r111 (6fh) write sequencer 3 0119h wseq_abort = 0 wseq_start = 1 wseq_start_index = 19h this starts the write sequenc er at index address 25 (19h) table 93 quick shutdown control the wseq_busy bit (in register r112, see tabl e 85) will be set to 1 while the sequence runs. when this bit returns to 0, the system clo ck can be disabled (clk_sys _ena=0) and mclk can be stopped.
pre-production WM8904 w pp, rev 3.3, september 2012 137 software reset and chip id a software reset can be commanded by writing to regi ster r0. this is a read-only register field and the contents will not be affected by writing to this register. the chip id can be read back from register r0. register address bit label default description r0 (00h) sw reset and id 15:0 sw_rst_de v_id1 [15:0] 8904h writing to this register resets all registers to their default state. reading from this register will indicate device id 8904h. table 94 software reset and chip id
WM8904 pre-production w pp, rev 3.3, september 2012 138 register map dec addr hex addr name 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bin default 0 0 0 sw reset and id 1000_1001_0000_0100 404bias control 0 00000000000 1 0bias_ena000 0_0000_0001_1000 505vmid control 0 000000000vmid_buf_ena000 vmid_ena000 0_0000_0000_0000 606mic bias control 0 000000000 m icdet_ena m icbias_ena 0000_0000_0000_0000 707mic bias control 1 0000000000000 0000_0000_0000_0000 100aanalogue adc 0 000000000000000adc_osr128000 0_0000_0000_0001 12 0 c po wer m anag ement 0 0 0 0 00000000000inl_enainr_ena000 0_0000_0000_0000 14 0 e po wer m anag ement 2 0 0 0 00000000000hpl_pga_enahpr_pga_ena000 0_0000_0000_0000 15 0 f po wer m anag ement 3 0 0 0 00000000000 lineoutl_pga_en a lineoutr_pga _e na 0000_0000_0000_0000 18 12 po wer m anag ement 6 0 0 0 000000000dacl_enadacr_enaadcl_enaadcr_ena000 0_0000_0000_0000 20 14 clock rates 0 1 toclk_rate_div1 6 toclk_rate_x40 11000 10 1111mclk_div1000_11 00_0101_1110 21 15 clock rates 1 0 0 0000000 0000_1100_0000_0101 2216clock rates 2 mclk_invsysclk_src0toclk_rate00000000opclk_enaclk_sys_enaclk_dsp_enatoclk_ena000 0_0000_0000_0000 24 18 audio interface 0 0 0 0 dacl_datinv dacr_datinv loopback aifadcl_src aifadcr_src aifdacl_src aifdacr_src adc_com p adc_com pm ode dac_com p d ac_com pm ode 0000_0000_0101_0000 25 19 audio interface 1 0 0 aifdac_tdm aifdac_tdm_ch an aifadc_tdm aifadc_tdm _ch an 0 aif_tris a if_b clk_inv bclk_dir 0 a if_lrclk_inv 0000_0000_0000_1010 26 1a audio interface 2 0 0 0 0 111 0000_0000_1110_0100 27 1b audio interface 3 0 0 0 0 lrclk_dir 0000_0000_0100_0000 301edac digital volume left 0000000dac_vu 0000_000p_1100_0000 311fdac digital volume right0000000dac_vu 0000_000p_1100_0000 32 20 dac digital 0 0 0 0 0 0000_0000_0000_0000 33 21 dac digital 1 0 0 0 dac_m ono dac_sb_filt dac_m uterate d ac_unm ute_ram 0 0 dac_osr128 0 0 dac_m ute 0 0000_0000_0000_1000 3624adc digital volume left 0000000adc_vu 0000_000p_1100_0000 3725adc digital volume right0000000adc_vu 0000_000p_1100_0000 3826adc digital 0 000000000 adc_hpf00adcl_datinvadcr_datinv000 0_0000_0001_0000 3927digital microphone 0 000dmic_enadmic_src00000000000000 0_0000_0000_0000 40 28 drc 0 drc_ena drc_dac_path 0 drc_ff_delay 0 drc_gs_ena drc_qr drc_anticlip drc_gs_hyst 00 00_0001_1010_1111 41 29 drc 1 0011_0010_0100_1000 422adrc 2 0000000000 0000_0000_0000_0000 432bdrc 3 00000 0000_0000_0000_0000 isel [ 1:0] lrclk_rate[10:0] drc_ knee_ op[ 4 :0] drc_hi_com p[ 2:0] drc_atk[3:0] drc_dcy[3:0] drc_m axgain[1:0] drc_knee_ ip[ 5:0 ] drc_m ingain[1:0] drc_qr_thr[1:0] drc_lo_com p[2:0] deem ph[ 1:0 ] aif_wl[1:0] dacr_vol[7:0] dacl_vol[7:0] aif_fm t[1:0] adcr_vol[7:0] drc_qr_dcy[1:0] adcl_vol[7:0] opclk_div[3:0] bclk_div [ 4:0] sw_rst_dev_id1[15:0] vm id_res[ 1:0] m icshort_thr[1:0] micdet_thr[2:0] m icb ia s_ sel[ 2 :0] clk_sy s_ ra te[ 3 :0] da c_b oost[ 1:0] sam ple_rate[2:0] adcl_dac_svol[3:0] drc_startup_gain[4:0] adcr_dac_svol[3:0] drc_ gs_ hy st_ lv l[ 1:0 ] adc_to_dacr[1:0] adc_to_dacl[1:0] adc_hpf_cut[1:0]
pre-production WM8904 w pp, rev 3.3, september 2012 139 dec addrhex addrname 1514131211109876543210 bin default 44 2c analogue left input 0 0 0 0 00000linmute00 0000_0000_1000_0101 45 2d analogue right input 0 0 0 0 00000rinmute00 0000_0000_1000_0101 46 2e analogue left input 1 0 0 0000000inl_cm_ena 0000_0000_0100_0100 47 2f analogue right input 1 0 0 0 000000inr_cm_ena 0000_0000_0100_0100 57 39 analogue out1 left 0 0 0 0000 hpoutl_mute hpout_vu hpoutlzc 0000_0000_p010_1101 58 3a analogue out1 right 0 0 0 0000 hpoutr_mute hpout_vu hpoutrzc 0000_0000_p010_1101 59 3b analogue out2 left 0 0 0 0000 lineoutl_mute lineout_vu lineoutlzc 0000_0000_p011_1001 60 3c analogue out2 right 0 0 0 0000 lineoutr_mute lineout_vu lineoutrzc 0000_0000_p011_1001 61 3d analogue out12 zc 0 0 0 000000000hpl_byp_enahpr_byp_ena lineoutl_byp_ ena lineoutr_byp _ena 0000_0000_0000_0000 6743dc servo 0 000000000000 dcs_ena_chan _3 dcs_ena_chan _2 dcs_ena_chan _1 dcs_ena_chan _0 0000_0000_0000_0000 68 44 dc servo 1 dcs_trig_sing le_3 dcs_trig_sing le_2 dcs_trig_sing le_1 dcs_trig_sing le_0 dcs_trig_seri es_3 dcs_trig_seri es_2 dcs_trig_seri es_1 dcs_trig_seri es_0 dcs_trig_sta rtup_3 dcs_trig_sta rtup_2 dcs_trig_sta rtup_1 dcs_trig_sta rtup_0 dcs_trig_dac _wr_3 dcs_trig_dac _wr_2 dcs_trig_dac _wr_1 dcs_trig_dac _wr_0 pppp_pppp_pppp_pppp 69 45 dc servo 2 0 0 0 0 0000 1010_1010_1010_1010 7147dc servo 4 000000000 1010_1010_1010_1010 7248dc servo 5 000000000 1010_1010_1010_1010 7349dc servo 6 00000000 0000_0000_0000_0000 744adc servo 7 00000000 0000_0000_0000_0000 754bdc servo 8 00000000 0000_0000_0000_0000 764cdc servo 9 00000000 0000_0000_0000_0000 77 4d dc servo readback 0 0 0 0 0 0000_0000_0000_0000 90 5a analogue hp 0 0 0 0 00000 hpl_rmv_sho rt hpl_ena_outp hpl_ena_dly hpl_ena hpr_rmv_sho rt hpr_ena_outp hpr_ena_dly hpr_ena 0000_0000_0000_0000 94 5e analogue lineout 0 0 0 0 00000 lineoutl_rmv _short lineoutl_ena_ outp lineoutl_ena_ dly lineoutl_ena lineoutr_rmv _short lineoutr_ena _outp lineoutr_ena _dly lineoutr_ena 0000_0000_0000_0000 9862charge pump 0 000000000000000cp_ena 0000_0000_0000_0000 104 68 class w 0 0000000000000 0 0 cp_dyn_pwr 0000_0000_0000_0100 108 6c write sequencer 0 0 0 0 0000wseq_ena000 0000_0000_0000_0000 109 6d write sequencer 1 0 0000_0000_0000_0000 110 6e write sequencer 2 0 wseq_eos 0 0 0000_0000_0000_0000 111 6f write sequencer 3 0 0 0 0 0 0 wseq_abort wseq_start 0 0 0000_0000_0000_0000 112 70 write sequencer 4 0 0 0 0 0 0 0 0 0 wseq_busy 0000_0000_0000_0000 dcs_dac_wr_val_2[7:0] wseq_data_width[2:0] wseq_data[7:0] wseq_data_start[3:0] wseq_start_index[5:0] dcs_series_no_23[6:0] l_mode[1:0] lin_vol[4:0] rin_vol[4:0] dcs_timer_period_01[3:0] hpoutl_vol[5:0] hpoutr_vol[5:0] dcs_timer_period_23[3:0] r_ip_sel_p[1:0] r_ip_sel_n[1:0] lineoutl_vol[5:0] dcs_series_no_01[6:0] dcs_dac_wr_val_3[7:0] dcs_dac_wr_val_1[7:0] r_mode[1:0] l_ip_sel_p[1:0] l_ip_sel_n[1:0] lineoutr_vol[5:0] wseq_delay[3:0] wseq_current_index[5:0] wseq_write_index[4:0] wseq_addr[7:0] dcs_dac_wr_val_0[7:0] dcs_dac_wr_complete[3:0] dcs_cal_complete[3:0] dcs_startup_complete[3:0]
WM8904 pre-production w pp, rev 3.3, september 2012 140 dec addrhex addrname 1514131211109876543210 bin default 11674fll control 1 0000000000000 fll_fracn_ena fll_osc_ena fll_ena 0000_0000_0000_0000 117 75 fll control 2 0 0 0 0 0000_0000_0000_0111 118 76 fll control 3 0000_0000_0000_0000 119 77 fll control 4 0 0 0010_1110_1110_0000 12078fll control 5 00000000000 1 0000_0000_0000_0100 121 79 gpio control 1 0000 000000 gpio1_pu gpio1_pd 0000_0000_0001_0100 122 7a gpio control 2 0000 000000 gpio2_pu gpio2_pd 0000_0000_0001_0000 123 7b gpio control 3 0000 000000 gpio3_pu gpio3_pd 0000_0000_0001_0000 124 7c gpio control 4 0000 0 0 gpi7_ena gpi8_ena gpio_bclk_mo de_ena 000 0000_0000_0000_0000 1267edigital pulls 00000000mclk_pumclk_pddacdat_pudacdat_pdlrclk_pulrclk_pdbclk_pubclk_pd 0000_0000_0000_0000 127 7f interrupt status 0 0 0 0 0 irq gpio_bclk_ein t wseq_eint gpio3_eint gpio2_eint gpio1_eint gpi8_eint gpi7_ein t fll_lock_eint mic_shrt_eint mic_det_eint xxxx_xppp_pppp_pppp 128 80 interrupt status mask 0 0 0 0 0 0 im_gpio_bclk_ eint im_wseq_eint im_gpio3_eint im_gpio2_eint im_gpio1_eint im_gpi8_eint im_gpi7_eint im_fll_lock_e int im_mic_shrt_e int im_mic_det_ei nt 1111_1111_1111_1111 129 81 interrupt polarity 0 0 0 0 0 0 gpio_bclk_ein t_pol wseq_eint_po l gpio3_eint_po l gpio2_eint_po l gpio1_eint_po l gpi8_eint_pol gpi7_eint_pol fll_lock_eint _pol mic_shrt_eint _pol mic_det_eint_ pol 0000_0000_0000_0000 130 82 interrupt debounce 0 0 0 0 0 0 gpio_bclk_ein t_db wseq_eint_db gpio3_eint_db gpio2_eint_db gpio1_eint_db gpi8_eint_db gpi7_eint_db fll_lock_eint _db mic_shrt_eint _db mic_det_eint_ db 0000_0000_0000_0000 13486eq1 000000000000000eq_ena 0000_0000_0000_0000 13587eq2 00000000000 0000_0000_0000_1100 13688eq3 00000000000 0000_0000_0000_1100 13789eq4 00000000000 0000_0000_0000_1100 1388aeq5 00000000000 0000_0000_0000_1100 1398beq6 00000000000 0000_0000_0000_1100 140 8c eq7 0000_1111_1100_1010 141 8d eq8 0000_0100_0000_0000 142 8e eq9 0000_0000_1101_1000 143 8f eq10 0001_1110_1011_0101 144 90 eq11 1111_0001_0100_0101 145 91 eq12 0000_1011_0111_0101 146 92 eq13 0000_0001_1100_0101 147 93 eq14 0001_1100_0101_1000 148 94 eq15 1111_0011_0111_0011 149 95 eq16 0000_1010_0101_0100 150 96 eq17 0000_0101_0101_1000 151 97 eq18 0001_0110_1000_1110 fll_clk_ref_div[1:0] fll_clk_ref_src[1:0] eq_b5_gain[4:0] eq_b1_a[15:0] gpio_bclk_sel[3:0] fll_ctrl_rate[2:0] fll_fratio[2:0] fll_k[15:0] fll_outdiv[5:0] eq_b3_a[15:0] eq_b2_b[15:0] eq_b2_c[15:0] eq_b3_gain[4:0] eq_b4_gain[4:0] fll_gain[3:0] gpio2_sel[3:0] eq_b1_pg[15:0] eq_b2_pg[15:0] eq_b1_gain[4:0] eq_b2_gain[4:0] eq_b1_b[15:0] eq_b3_c[15:0] eq_b3_b[15:0] fll_n[9:0] eq_b2_a[15:0] gpio1_sel[3:0] gpio3_sel[3:0] eq_b4_a[15:0] eq_b3_pg[15:0]
pre-production WM8904 w pp, rev 3.3, september 2012 141 dec addrhex addrname 1514131211109876543210 bin default 152 98 eq19 1111_1000_0010_1001 153 99 eq20 0000_0111_1010_1101 154 9a eq21 0001_0001_0000_0011 155 9b eq22 0000_0101_0110_0100 156 9c eq23 0000_0101_0101_1001 157 9d eq24 0100_0000_0000_0000 198c6adc test 0 0000000000000 adc_128_osr_ tst_mode 0 adc_bi asx1p5 0000_0000_0000_0000 247f7fll nco test 0 000000000000000 fll_frc_nco 0000_0000_0000_0000 248f8fll nco test 1 0000000000 0000_0000_0001_1001 eq_b4_pg[15:0] eq_b5_b[15:0] eq_b5_pg[15:0] eq_b4_c[15:0] eq_b5_a[15:0] eq_b4_b[15:0] fll_frc_nco_val[5:0]
WM8904 pre-production w pp, rev 3.3, september 2012 142 register bits by address register address bit label default description refer to r0 (00h) sw reset and id 15:0 sw_rst_dev _id1 [15:0] 1000_1001 _0000_010 0 writing to this register resets all registers to their default state. reading from this register will indicate device id 8904h. software reset and chip id register 00h sw reset and id register address bit label default description refer to r4 (04h) bias control 0 3:2 isel [1:0] 10 master bias control 00 = low power bias 01 = reserved 10 = high performance bias (default) 11 = reserved note that the isel register should only be changed as part of the low power mode enable/disable sequences. reference voltages and master bias 0 bias_ena 0 enables the normal bias current generator (for all analogue functions) 0 = disabled 1 = enabled reference voltages and master bias register 04h bias control 0 register address bit label default description refer to r5 (05h) vmid control 0 6 vmid_buf_en a 0 enable vmid buffer to unused inputs/outputs 0 = disabled 1 = enabled analogue outputs 2:1 vmid_res [1:0] 00 vmid divider enable and select 00 = vmid disabled (for off mode) 01 = 2 x 50k divider (for normal operation) 10 = 2 x 250k divider (for low power standby) 11 = 2 x 5k divider (for fast start-up) analogue outputs 0 vmid_ena 0 vmid buffer enable 0 = disabled 1 = enabled analogue outputs register 05h vmid control 0
pre-production WM8904 w pp, rev 3.3, september 2012 143 register address bit label default description refer to r6 (06h) mic bias control 0 6:4 micdet_thr [2:0] 000 micbias current detect threshold (avdd = 1.8v) 000 = 0.070ma 001 = 0.260ma 010 = 0.450ma 011 = 0.640ma 100 = 0.830ma 101 = 1.020ma 110 = 1.210ma 111 = 1.400ma note that the value scales with avdd. the value quoted is correct for avdd=1.8v. electret condenser microphone interface 3:2 micshort_t hr [1:0] 00 micbias short circuit th reshold (avdd = 1.8v) 00 = 0.520ma 01 = 0.880ma 10 = 1.240ma 11 = 1.600ma note that the value scales with avdd. the value quoted is correct for avdd=1.8v. electret condenser microphone interface 1 micdet_ena 0 micbias current and short circuit detect enable 0 = disabled 1 = enabled electret condenser microphone interface 0 micbias_ena 0 micbias enable 0 = disabled 1 = enabled electret condenser microphone interface register 06h mic bias control 0 register address bit label default description refer to r7 (07h) mic bias control 1 2:0 micbias_sel [2:0] 000 selects micbias voltage 000 = 9/10 x avdd (1.6v) 001 = 10/9 x avdd (2.0v) 010 = 7/6 x avdd (2.1v) 011 = 4/3 x avdd (2.4v) 100 to 111 = 3/2 x avdd (2.7v) note that the voltage scales with avdd. the value quoted in brackets is correct for avdd=1.8v. electret condenser microphone interface register 07h mic bias control 1
WM8904 pre-production w pp, rev 3.3, september 2012 144 register address bit label default description refer to r10 (0ah) analogue adc 0 0 adc_osr128 1 adc oversampling ratio 0 = low power (64 x fs) 1 = high performance (128 x fs) adc oversampling ratio (osr) register 0ah analogue adc 0 register address bit label default description refer to r12 (0ch) power management 0 1 inl_ena 0 left input pga enable 0 = disabled 1 = enabled input pga enable 0 inr_ena 0 right input pga enable 0 = disabled 1 = enabled input pga enable register 0ch power management 0 register address bit label default description refer to r14 (0eh) power management 2 1 hpl_pga_en a 0 left headphone output enable 0 = disabled 1 = enabled output signal paths enable 0 hpr_pga_en a 0 right headphone output enable 0 = disabled 1 = enabled output signal paths enable register 0eh power management 2 register address bit label default description refer to r15 (0fh) power management 3 1 lineoutl_pg a_ena 0 left line output enable 0 = disabled 1 = enabled output signal paths enable 0 lineoutr_pg a_ena 0 right line output enable 0 = disabled 1 = enabled output signal paths enable register 0fh power management 3 register address bit label default description refer to r18 (12h) power management 6 3 dacl_ena 0 left dac enable 0 = dac disabled 1 = dac enabled digital-to- analogue converter (dac) 2 dacr_ena 0 right dac enable 0 = dac disabled 1 = dac enabled digital-to- analogue converter (dac) 1 adcl_ena 0 left adc enable 0 = disabled 1 = enabled digital-to- analogue converter (dac) 0 adcr_ena 0 right adc enable 0 = disabled 1 = enabled digital-to- analogue converter (dac) register 12h power management 6
pre-production WM8904 w pp, rev 3.3, september 2012 145 register address bit label default description refer to r20 (14h) clock rates 0 14 toclk_rate _div16 0 toclk rate divider (/16) 0 = f / 1 1 = f / 16 clocking and sample rates 13 toclk_rate _x4 0 toclk rate multiplier 0 = f x 1 1 = f x 4 clocking and sample rates 0 mclk_div 0 enables divide by 2 on mclk 0 = sysclk = mclk 1 = sysclk = mclk / 2 clocking and sample rates register 14h clock rates 0 register address bit label default description refer to r21 (15h) clock rates 1 13:10 clk_sys_rat e [3:0] 0011 selects the sysclk / fs ratio 0000 = 64 0001 = 128 0010 = 192 0011 = 256 0100 = 384 0101 = 512 0110 = 768 0111 = 1024 1000 = 1408 1001 = 1536 clocking and sample rates 2:0 sample_rat e [2:0] 101 selects the sample rate (fs) 000 = 8khz 001 = 11.025khz, 12khz 010 = 16khz 011 = 22.05khz, 24khz 100 = 32khz 101 = 44.1khz, 48khz 110 to 111 = reserved clocking and sample rates register 15h clock rates 1 register address bit label default description refer to r22 (16h) clock rates 2 15 mclk_inv 0 mclk invert 0 = mclk not inverted 1 = mclk inverted clocking and sample rates 14 sysclk_src 0 sysclk source select 0 = mclk 1 = fll output clocking and sample rates 12 toclk_rate 0 toclk rate divider (/2) 0 = f / 2 1 = f / 1 clocking and sample rates 3 opclk_ena 0 gpio clock output enable 0 = disabled 1 = enabled clocking and sample rates 2 clk_sys_en a 0 system clock enable 0 = disabled 1 = enabled clocking and sample rates
WM8904 pre-production w pp, rev 3.3, september 2012 146 register address bit label default description refer to 1 clk_dsp_en a 0 dsp clock enable 0 = disabled 1 = enabled clocking and sample rates 0 toclk_ena 0 zero cross timeout enable 0 = disabled 1 = enabled clocking and sample rates register 16h clock rates 2 register address bit label default description refer to r24 (18h) audio interface 0 12 dacl_datinv 0 left dac invert 0 = left dac output not inverted 1 = left dac output inverted digital mixing 11 dacr_datinv 0 right dac invert 0 = right dac output not inverted 1 = right dac output inverted digital mixing 10:9 dac_boost [1:0] 00 dac digital input volume boost 00 = 0db 01 = +6db (input data must not exceed -6dbfs) 10 = +12db (input data must not exceed -12dbfs) 11 = +18db (input data must not exceed -18dbfs) digital mixing 8 loopback 0 digital loopback function 0 = no loopback 1 = loopback enabled (adc data output is directly input to dac data input) digital audio interface control 7 aifadcl_src 0 left digital audio channel source 0 = left adc data is output on left channel 1 = right adc data is output on left channel digital audio interface control 6 aifadcr_src 1 right digital audio channel source 0 = left adc data is output on right channel 1 = right adc data is output on right channel digital audio interface control 5 aifdacl_src 0 left dac data source select 0 = left dac outputs left channel data 1 = left dac outputs right channel data digital audio interface control 4 aifdacr_src 1 right dac data source select 0 = right dac outputs left channel data 1 = right dac outputs right channel data digital audio interface control 3 adc_comp 0 adc companding enable 0 = disabled 1 = enabled digital audio interface control 2 adc_compmo de 0 adc companding type 0 = -law 1 = a-law digital audio interface control 1 dac_comp 0 dac companding enable 0 = disabled 1 = enabled digital audio interface control 0 dac_compmo de 0 dac companding type 0 = -law 1 = a-law digital audio interface control register 18h audio interface 0
pre-production WM8904 w pp, rev 3.3, september 2012 147 register address bit label default description refer to r25 (19h) audio interface 1 13 aifdac_tdm 0 dac tdm enable 0 = normal dacdat operation 1 = tdm enabled on dacdat digital audio interface control 12 aifdac_tdm_ chan 0 dacdat tdm channel select 0 = dacdat data input on slot 0 1 = dacdat data input on slot 1 digital audio interface control 11 aifadc_tdm 0 adc tdm enable 0 = normal adcdat operation 1 = tdm enabled on adcdat digital audio interface control 10 aifadc_tdm_ chan 0 adcdat tdm channel select 0 = adcdat outputs data on slot 0 1 = adcdat output data on slot 1 digital audio interface control 8 aif_tris 0 audio interface tristate 0 = audio interface pins operate normally 1 = tristate all audio interface pins digital audio interface control 7 aif_bclk_inv 0 bclk invert 0 = bclk not inverted 1 = bclk inverted digital audio interface control 6 bclk_dir 0 audio interface bclk direction 0 = bclk is input 1 = bclk is output digital audio interface control 4 aif_lrclk_in v 0 lrc polarity / dsp mode a-b select. right, left and i2s modes ? lrc polarity 0 = not inverted 1 = inverted dsp mode ? mode a-b select 0 = msb is available on 2nd bclk rising edge after lrc rising edge (mode a) 1 = msb is available on 1s t bclk rising edge after lrc rising edge (mode b) digital audio interface control 3:2 aif_wl [1:0] 10 digital audio interface word length 00 = 16 bits 01 = 20 bits 10 = 24 bits 11 = 32 bits digital audio interface control 1:0 aif_fmt [1:0] 10 digital audio interface format 00 = right justified 01 = left justified 10 = i2s 11 = dsp digital audio interface control register 19h audio interface 1
WM8904 pre-production w pp, rev 3.3, september 2012 148 register address bit label default description refer to r26 (1ah) audio interface 2 11:8 opclk_div [3:0] 0000 gpio output clock divider 0000 = sysclk 0001 = sysclk / 2 0010 = sysclk / 3 0011 = sysclk / 4 0100 = sysclk / 5.5 0101 = sysclk / 6 0110 = sysclk / 8 0111 = sysclk / 12 1000 = sysclk / 16 1001 to 1111 = reserved digital audio interface control 4:0 bclk_div [4:0] 0_0100 bclk frequency (master mode) 00000 = sysclk 00001 = sysclk / 1.5 00010 = sysclk / 2 00011 = sysclk / 3 00100 = sysclk / 4 (default) 00101 = sysclk / 5 00110 = sysclk / 5.5 00111 = sysclk / 6 01000 = sysclk / 8 01001 = sysclk / 10 01010 = sysclk / 11 01011 = sysclk / 12 01100 = sysclk / 16 01101 = sysclk / 20 01110 = sysclk / 22 01111 = sysclk / 24 10000 = sysclk / 25 10001 = sysclk / 30 10010 = sysclk / 32 10011 = sysclk / 44 10100 = sysclk / 48 digital audio interface control register 1ah audio interface 2 register address bit label default description refer to r27 (1bh) audio interface 3 11 lrclk_dir 0 audio interface lrc direction 0 = lrc is input 1 = lrc is output digital audio interface control 10:0 lrclk_rate [10:0] 000_0100_ 0000 lrc rate (master mode) lrc clock output = bclk / lrclk_rate integer (lsb = 1) valid range: 8 to 2047 digital audio interface control register 1bh audio interface 3
pre-production WM8904 w pp, rev 3.3, september 2012 149 register address bit label default description refer to r30 (1eh) dac digital volume left 8 dac_vu 0 dac volume update writing a 1 to this bit causes left and right dac volume to be updated simultaneously dac digital volume control 7:0 dacl_vol [7:0] 1100_0000 left dac digital volume 00h = mute 01h = -71.625db 02h = -71.250db ? (0.375db steps) c0h to ffh = 0db dac digital volume control register 1eh dac digital volume left register address bit label default description refer to r31 (1fh) dac digital volume right 8 dac_vu 0 dac volume update writing a 1 to this bit causes left and right dac volume to be updated simultaneously dac digital volume control 7:0 dacr_vol [7:0] 1100_0000 right dac digital volume 00h = mute 01h = -71.625db 02h = -71.250db ? (0.375db steps) c0h to ffh = 0db dac digital volume control register 1fh dac digital volume right register address bit label default description refer to r32 (20h) dac digital 0 11:8 adcl_dac_s vol [3:0] 0000 left digital sidetone volume 0000 = -36db 0001 = -33db (? 3db steps) 1011 = -3db 11xx = 0db digital mixing 7:4 adcr_dac_s vol [3:0] 0000 right digital sidetone volume 0000 = -36db 0001 = -33db (? 3db steps) 1011 = -3db 11xx = 0db digital mixing 3:2 adc_to_dac l [1:0] 00 left dac digital sidetone source 00 = no sidetone 01 = left adc 10 = right adc 11 = reserved digital mixing 1:0 adc_to_dac r [1:0] 00 right dac digital sidetone source 00 = no sidetone 01 = left adc 10 = right adc 11 = reserved digital mixing register 20h dac digital 0
WM8904 pre-production w pp, rev 3.3, september 2012 150 register address bit label default description refer to r33 (21h) dac digital 1 12 dac_mono 0 dac mono mix 0 = stereo 1 = mono (mono mix output on enabled dac) dac mono mix 11 dac_sb_filt 0 selects dac filter characteristics 0 = normal mode 1 = sloping stopband mode (recommended when fs ??? 24khz ? dac sloping stopband filter 10 dac_mutera te 0 dac soft mute ramp rate 0 = fast ramp (fs/2, maximum ramp time is 10.7ms at fs=48k) 1 = slow ramp (fs/32, maximum ramp time is 171ms at fs=48k) dac soft mute and soft un-mute 9 dac_unmute _ramp 0 dac soft mute mode 0 = disabling soft-mute (dac_mute=0) will cause the dac volume to change immediately to dacl_vol and dacr_vol settings 1 = disabling soft-mute (dac_mute=0) will cause the dac volume to ramp up gradually to the dacl_vol and dacr_vol settings dac soft mute and soft un-mute 6 dac_osr128 0 dac oversample rate select 0 = low power (normal osr) 1 = high performance (double osr) dac oversampling ratio (osr) 3 dac_mute 1 dac soft mute control 0 = dac un-mute 1 = dac mute dac soft mute and soft un-mute 2:1 deemph [1:0] 00 dac de-emphasis control 00 = no de-emphasis 01 = 32khz sample rate 10 = 44.1khz sample rate 11 = 48khz sample rate dac de-emphasis register 21h dac digital 1 register address bit label default description refer to r36 (24h) adc digital volume left 8 adc_vu 0 adc volume update writing a 1 to this bit causes left and right adc volume to be updated simultaneously analogue-to-digital converter (adc) 7:0 adcl_vol [7:0] 1100_0000 left adc digital volume 00h = mute 01h = -71.625db 02h = -71.250db ? (0.375db steps) c0h = 0db ? (0.375db steps) efh to ffh = +17.625db analogue-to-digital converter (adc) register 24h adc digital volume left
pre-production WM8904 w pp, rev 3.3, september 2012 151 register address bit label default description refer to r37 (25h) adc digital volume right 8 adc_vu 0 adc volume update writing a 1 to this bit causes left and right adc volume to be updated simultaneously analogue-to-digital converter (adc) 7:0 adcr_vol [7:0] 1100_0000 right adc digital volume 00h = mute 01h = -71.625db 02h = -71.250db ? (0.375db steps) c0h = 0db ? (0.375db steps) efh to ffh = +17.625db analogue-to-digital converter (adc) register 25h adc digital volume right register address bit label default description refer to r38 (26h) adc digital 0 6:5 adc_hpf_cu t [1:0] 00 adc digital high pass filt er cut-off frequency (fc) 00 = hi-fi mode (fc=4hz at fs=48khz) 01 = voice mode 1 (fc=127hz at fs=16khz) 10 = voice mode 2 (fc=130hz at fs=8khz) 11 = voice mode 3 (fc=267hz at fs=8khz) (note: fc scales with sample rate fs.) analogue-to- digital converter (adc) 4 adc_hpf 1 adc digital high pass filter enable 0 = disabled 1 = enabled analogue-to- digital converter (adc) 1 adcl_datinv 0 left adc invert 0 = left adc output not inverted 1 = left adc output inverted analogue-to- digital converter (adc) 0 adcr_datin v 0 right adc invert 0 = right adc output not inverted 1 = right adc output inverted analogue-to- digital converter (adc) register 26h adc digital 0 register address bit label default description refer to r39 (27h) digital microphone 0 12 dmic_ena 0 enables digital microphone mode 0 = audio dsp input is from adc 1 = audio dsp input is from digital microphone interface when dmic_ena = 0, the digital microphone clock (dmicclk) is held low. digital microphone interface 11 dmic_src 0 selects digital microphone data input pin 0 = in1l/dmicdat1 1 = in1r/dmicdat2 digital microphone interface register 27h digital microphone 0
WM8904 pre-production w pp, rev 3.3, september 2012 152 register address bit label default description refer to r40 (28h) drc 0 15 drc_ena 0 drc enable 1 = enabled 0 = disabled dynamic range control (drc) 14 drc_dac_pat h 0 drc path select 0 = adc path 1 = dac path dynamic range control (drc) 12:11 drc_gs_hyst _lvl [1:0] 00 gain smoothing hysteresis threshold 00 = low 01 = medium (recommended) 10 = high 11 = reserved dynamic range control (drc) 10:6 drc_startup _gain [4:0] 0_0110 initial gain at drc startup 00000 = -3db 00001 = -2.5db 00010 = -2db 00011 = -1.5db 00100 = -1db 00101 = -0.5db 00110 = 0db (default) 00111 = 0.5db 01000 = 1db 01001 = 1.5db 01010 = 2db 01011 = 2.5db 01100 = 3db 01101 = 3.5db 01110 = 4db 01111 = 4.5db 10000 = 5db 10001 = 5.5db 10010 = 6db 10011 to 11111 = reserved dynamic range control (drc) 5 drc_ff_delay 1 feed-forward delay for anti-clip feature 0 = 5 samples 1 = 9 samples time delay can be calculated as 5/fs or 9/ fs, where fs is the sample rate. dynamic range control (drc) 3 drc_gs_ena 1 gain smoothing enable 0 = disabled 1 = enabled dynamic range control (drc) 2 drc_qr 1 quick release enable 0 = disabled 1 = enabled dynamic range control (drc) 1 drc_anticlip 1 anti-clip enable 0 = disabled 1 = enabled dynamic range control (drc) 0 drc_gs_hyst 1 gain smoothing hysteresis enable 0 = disabled 1 = enabled dynamic range control (drc) register 28h drc 0
pre-production WM8904 w pp, rev 3.3, september 2012 153 register address bit label default description refer to r41 (29h) drc 1 15:12 drc_atk [3:0] 0011 gain attack rate (seconds/6db) 0000 = reserved 0001 = 182s 0010 = 363s 0011 = 726s (default) 0100 = 1.45ms 0101 = 2.9ms 0110 = 5.8ms 0111 = 11.6ms 1000 = 23.2ms 1001 = 46.4ms 1010 = 92.8ms 1011-1111 = reserved dynamic range control (drc) 11:8 drc_dcy [3:0] 0010 gain decay rate (seconds/6db) 0000 = 186ms 0001 = 372ms 0010 = 743ms (default) 0011 = 1.49s 0100 = 2.97s 0101 = 5.94s 0110 = 11.89s 0111 = 23.78s 1000 = 47.56s 1001-1111 = reserved dynamic range control (drc) 7:6 drc_qr_thr [1:0] 01 quick release crest factor threshold 00 = 12db 01 = 18db (default) 10 = 24db 11 = 30db dynamic range control (drc) 5:4 drc_qr_dcy [1:0] 00 quick release decay rate (seconds/6db) 00 = 0.725ms (default) 01 = 1.45ms 10 = 5.8ms 11 = reserved dynamic range control (drc) 3:2 drc_mingain [1:0] 10 minimum gain the drc can use to attenuate audio signals 00 = 0db (default) 01 = -6db 10 = -12db 11 = -18db dynamic range control (drc) 1:0 drc_maxgain [1:0] 00 maximum gain the drc can use to boost audio signals 00 = 12db 01 = 18db (default) 10 = 24db 11 = 36db dynamic range control (drc) register 29h drc 1
WM8904 pre-production w pp, rev 3.3, september 2012 154 register address bit label default description refer to r42 (2ah) drc 2 5:3 drc_hi_com p [2:0] 000 compressor slope (upper region) 000 = 1 (no compression) 001 = 1/2 010 = 1/4 011 = 1/8 100 = 1/16 101 = 0 110 to 111 = reserved dynamic range control (drc) 2:0 drc_lo_com p [2:0] 000 compressor slope (lower region) 000 = 1 (no compression) 001 = 1/2 010 = 1/4 011 = 1/8 100 = 0 101 to 111 = reserved dynamic range control (drc) register 2ah drc 2 register address bit label default description refer to r43 (2bh) drc 3 10:5 drc_knee_ip [5:0] 00_0000 input signal at the compressor 'knee'. 000000 = 0db 000001 = -0.75db 000010 = -1.5db ? (-0.75db steps) 111100 = -45db 111101 to 111111 = reserved dynamic range control (drc) 4:0 drc_knee_o p [4:0] 0_0000 output signal at the compressor 'knee'. 00000 = 0db 00001 = -0.75db 00010 = -1.5db ? (-0.75db steps) 11110 = -22.5db 11111 = reserved dynamic range control (drc) register 2bh drc 3
pre-production WM8904 w pp, rev 3.3, september 2012 155 register address bit label default description refer to r44 (2ch) analogue left input 0 7 linmute 1 left input pga mute 0 = not muted 1 = muted input pga gain control 4:0 lin_vol [4:0] 0_0101 left input pga volume if l_mode = 00 (single ended) or l_mode = 01 (differential line) 00000 = -1.5 db 00001 = -1.3 db 00010 = -1.0 db 00011 = -0.7 db 00100 = -0.3 db 00101 = +0.0 db (default) 00110 = +0.3 db 00111 = +0.7 db 01000 = +1.0 db 01001 = +1.4 db 01010 = +1.8 db 01011 = +2.3 db 01100 = +2.7 db 01101 = +3.2 db 01110 = +3.7 db 01111 = +4.2 db 10000 = +4.8 db 10001 = +5.4 db 10010 = +6.0 db 10011 = +6.7 db 10100 = +7.5 db 10101 = +8.3 db 10110 = +9.2 db 10111 = +10.2 db 11000 = +11.4 db 11001 = +12.7 db 11010 = +14.3 db 11011 = +16.2 db 11100 = +19.2 db 11101 = +22.3 db 11110 = +25.2 db 11111 = +28.3 db if l_mode = 10 (differential mic) 00000 = reserved 00001 = +12 db 00010 = +15 db 00011 = +18 db 00100 = +21 db 00101 = +24 db (default) 00110 = +27 db 00111 to 11111 = +30 db input pga gain control register 2ch analogue left input 0
WM8904 pre-production w pp, rev 3.3, september 2012 156 register address bit label default description refer to r45 (2dh) analogue right input 0 7 rinmute 1 right input pga mute 0 = not muted 1 = muted input pga gain control 4:0 rin_vol [4:0] 0_0101 right input pga volume if r_mode = 00 (single ended) or r_mode = 01 (differential line) 00000 = -1.5 db 00001 = -1.3 db 00010 = -1.0 db 00011 = -0.7 db 00100 = -0.3 db 00101 = +0.0 db (default) 00110 = +0.3 db 00111 = +0.7 db 01000 = +1.0 db 01001 = +1.4 db 01010 = +1.8 db 01011 = +2.3 db 01100 = +2.7 db 01101 = +3.2 db 01110 = +3.7 db 01111 = +4.2 db 10000 = +4.8 db 10001 = +5.4 db 10010 = +6.0 db 10011 = +6.7 db 10100 = +7.5 db 10101 = +8.3 db 10110 = +9.2 db 10111 = +10.2 db 11000 = +11.4 db 11001 = +12.7 db 11010 = +14.3 db 11011 = +16.2 db 11100 = +19.2 db 11101 = +22.3 db 11110 = +25.2 db 11111 = +28.3 db if r_mode = 10 (differential mic) 00000 = reserved 00001 = +12 db 00010 = +15 db 00011 = +18 db 00100 = +21 db 00101 = +24 db (default) 00110 = +27 db 00111 to 11111 = +30 db input pga gain control register 2dh analogue right input 0
pre-production WM8904 w pp, rev 3.3, september 2012 157 register address bit label default description refer to r46 (2eh) analogue left input 1 6 inl_cm_ena 1 left input pga common mode rejection enable 0 = disabled 1 = enabled (only available for l_mode=01 ? differential line) input pga common mode amplifier 5:4 l_ip_sel_n [1:0] 00 in single-ended or different ial line modes, this field selects the input pin for the inverting side of the left input path. in differential mic mode, this field selects the input pin for the non-inverting side of the left input path. 00 = in1l 01 = in2l 1x = in3l analogue input signal path 3:2 l_ip_sel_p [1:0] 01 in single-ended or different ial line modes, this field selects the input pin for the non-inverting side of the left input path. in differential mic mode, this field selects the input pin for the inverting side of the left input path. 00 = in1l 01 = in2l 1x = in3l analogue input signal path 1:0 l_mode [1:0] 00 sets the mode for the left analogue input: 00 = single-ended 01 = differential line 10 = differential mic 11 = reserved analogue input signal path register 2eh analogue left input 1 register address bit label default description refer to r47 (2fh) analogue right input 1 6 inr_cm_ena 1 right input pga common mode rejection enable 0 = disabled 1 = enabled (only available for r_mode =01 ? differential line) input pga common mode amplifier 5:4 r_ip_sel_n [1:0] 00 in single-ended or different ial line modes, this field selects the input pin for the inverting side of the right input path. in differential mic mode, this field selects the input pin for the non-inverting side of the right input path. 00 = in1r 01 = in2r 1x = in3r analogue input signal path 3:2 r_ip_sel_p [1:0] 01 in single-ended or different ial line modes, this field selects the input pin for the non-inverting side of the right input path. in differential mic mode, this field selects the input pin for the inverting side of the right input path. 00 = in1r 01 = in2r 1x = in3r analogue input signal path 1:0 r_mode [1:0] 00 sets the mode for the right analogue input: 00 = single-ended 01 = differential line 10 = differential mic 11 = reserved analogue input signal path register 2fh analogue right input 1
WM8904 pre-production w pp, rev 3.3, september 2012 158 register address bit label default description refer to r57 (39h) analogue out1 left 8 hpoutl_mut e 0 left headphone output mute 0 = un-mute 1 = mute output volume control 7 hpout_vu 0 headphone output volume update writing a 1 to this bit will update hpoutl and hpoutr volumes simultaneously. output volume control 6 hpoutlzc 0 left headphone output zero cross enable 0 = disabled 1 = enabled output volume control 5:0 hpoutl_vol [5:0] 10_1101 left headphone output volume 000000 = -57db 000001 = -56db (? 1db steps) 111001 = 0db (? 1db steps) 111110 = +5db 111111 = +6db output volume control register 39h analogue out1 left register address bit label default description refer to r58 (3ah) analogue out1 right 8 hpoutr_mut e 0 right headphone output mute 0 = un-mute 1 = mute output volume control 7 hpout_vu 0 headphone output volume update writing a 1 to this bit will update hpoutl and hpoutr volumes simultaneously. output volume control 6 hpoutrzc 0 right headphone output zero cross enable 0 = disabled 1 = enabled output volume control 5:0 hpoutr_vol [5:0] 10_1101 right headphone output volume 000000 = -57db 000001 = -56db (? 1db steps) 111001 = 0db (? 1db steps) 111110 = +5db 111111 = +6db output volume control register 3ah analogue out1 right
pre-production WM8904 w pp, rev 3.3, september 2012 159 register address bit label default description refer to r59 (3bh) analogue out2 left 8 lineoutl_mu te 0 left line output mute 0 = un-mute 1 = mute output volume control 7 lineout_vu 0 line output volume update writing a 1 to this bit will update lineoutl and lineoutr volumes simultaneously. output volume control 6 lineoutlzc 0 left line output zero cross enable 0 = disabled 1 = enabled output volume control 5:0 lineoutl_vo l [5:0] 11_1001 left line output volume 000000 = -57db 000001 = -56db (? 1db steps) 111001 = 0db (? 1db steps) 111110 = +5db 111111 = +6db output volume control register 3bh analogue out2 left register address bit label default description refer to r60 (3ch) analogue out2 right 8 lineoutr_m ute 0 right line output mute 0 = un-mute 1 = mute output volume control 7 lineout_vu 0 line output volume update writing a 1 to this bit will update lineoutl and lineoutr volumes simultaneously. output volume control 6 lineoutrzc 0 right line output zero cross enable 0 = disabled 1 = enabled output volume control 5:0 lineoutr_vo l [5:0] 11_1001 right line output volume 000000 = -57db 000001 = -56db (? 1db steps) 111001 = 0db (? 1db steps) 111110 = +5db 111111 = +6db output volume control register 3ch analogue out2 right
WM8904 pre-production w pp, rev 3.3, september 2012 160 register address bit label default description refer to r61 (3dh) analogue out12 zc 3 hpl_byp_en a 0 selects input for left headphone output mux 0 = left dac 1 = left input pga (analogue bypass) output signal paths enable 2 hpr_byp_en a 0 selects input for right headphone output mux 0 = right dac 1 = right input pga (analogue bypass) output signal paths enable 1 lineoutl_by p_ena 0 selects input for left line output mux 0 = left dac 1 = left input pga (analogue bypass) output signal paths enable 0 lineoutr_by p_ena 0 selects input for right line output mux 0 = right dac 1 = right input pga (analogue bypass) output signal paths enable register 3dh analogue out12 zc register address bit label default description refer to r67 (43h) dc servo 0 3 dcs_ena_ch an_3 0 dc servo enable for lineoutr 0 = disabled 1 = enabled dc servo 2 dcs_ena_ch an_2 0 dc servo enable for lineoutl 0 = disabled 1 = enabled dc servo 1 dcs_ena_ch an_1 0 dc servo enable for hpoutr 0 = disabled 1 = enabled dc servo 0 dcs_ena_ch an_0 0 dc servo enable for hpoutl 0 = disabled 1 = enabled dc servo register 43h dc servo 0 register address bit label default description refer to r68 (44h) dc servo 1 15 dcs_trig_si ngle_3 0 writing 1 to this bit selects a single dc offset correction for lineoutr. in readback, a value of 1 indicates that the dc servo single correction is in progress. dc servo 14 dcs_trig_si ngle_2 0 writing 1 to this bit selects a single dc offset correction for lineoutl. in readback, a value of 1 indicates that the dc servo single correction is in progress. dc servo 13 dcs_trig_si ngle_1 0 writing 1 to this bit selects a single dc offset correction for hpoutr. in readback, a value of 1 indicates that the dc servo single correction is in progress. dc servo 12 dcs_trig_si ngle_0 0 writing 1 to this bit selects a single dc offset correction for hpoutl. in readback, a value of 1 indicates that the dc servo single correction is in progress. dc servo 11 dcs_trig_se ries_3 0 writing 1 to this bit selects a series of dc offset corrections for lineoutr. in readback, a value of 1 indicates that the dc servo dac write correction is in progress. dc servo
pre-production WM8904 w pp, rev 3.3, september 2012 161 register address bit label default description refer to 10 dcs_trig_se ries_2 0 writing 1 to this bit selects a series of dc offset corrections for lineoutl. in readback, a value of 1 indicates that the dc servo dac write correction is in progress. dc servo 9 dcs_trig_se ries_1 0 writing 1 to this bit selects a series of dc offset corrections for hpoutr. in readback, a value of 1 indicates that the dc servo dac write correction is in progress. dc servo 8 dcs_trig_se ries_0 0 writing 1 to this bit selects a series of dc offset corrections for hpoutl. in readback, a value of 1 indicates that the dc servo dac write correction is in progress. dc servo 7 dcs_trig_st artup_3 0 writing 1 to this bit selects start-up dc servo mode for lineoutr. in readback, a value of 1 indicates that the dc servo start-up correction is in progress. dc servo 6 dcs_trig_st artup_2 0 writing 1 to this bit selects start-up dc servo mode for lineoutl. in readback, a value of 1 indicates that the dc servo start-up correction is in progress. dc servo 5 dcs_trig_st artup_1 0 writing 1 to this bit selects start-up dc servo mode for hpoutr. in readback, a value of 1 indicates that the dc servo start-up correction is in progress. dc servo 4 dcs_trig_st artup_0 0 writing 1 to this bit selects start-up dc servo mode for hpoutl. in readback, a value of 1 indicates that the dc servo start-up correction is in progress. dc servo 3 dcs_trig_da c_wr_3 0 writing 1 to this bit selects dac write dc servo mode for lineoutr. in readback, a value of 1 indicates that the dc servo dac write correction is in progress. dc servo 2 dcs_trig_da c_wr_2 0 writing 1 to this bit selects dac write dc servo mode for lineoutl. in readback, a value of 1 indicates that the dc servo dac write correction is in progress. dc servo 1 dcs_trig_da c_wr_1 0 writing 1 to this bit selects dac write dc servo mode for hpoutr. in readback, a value of 1 indicates that the dc servo dac write correction is in progress. dc servo 0 dcs_trig_da c_wr_0 0 writing 1 to this bit selects dac write dc servo mode for hpoutl. in readback, a value of 1 indicates that the dc servo dac write correction is in progress. dc servo register 44h dc servo 1
WM8904 pre-production w pp, rev 3.3, september 2012 162 register address bit label default description refer to r69 (45h) dc servo 2 11:8 dcs_timer_pe riod_23 [3:0] 1010 time between periodic updates for lineoutl/lineoutr. time is calculated as 0.256s x (2^period) 0000 = off 0001 = 0.52s 1010 = 266s (4min 26s) 1111 = 8519s (2hr 22s) dc servo 3:0 dcs_timer_pe riod_01 [3:0] 1010 time between periodic updates for hpoutl/hpoutr. time is calculated as 0.256s x (2^period) 0000 = off 0001 = 0.52s 1010 = 266s (4min 26s) 1111 = 8519s (2hr 22s) dc servo register 45h dc servo 2 register address bit label default description refer to r71 (47h) dc servo 4 6:0 dcs_series_n o_23 [6:0] 010_1010 number of dc servo updates to perform in a series event for lineoutl/lineoutr. 0 = 1 updates 1 = 2 updates ... 127 = 128 updates dc servo register 47h dc servo 4 register address bit label default description refer to r72 (48h) dc servo 5 6:0 dcs_series_n o_01 [6:0] 010_1010 number of dc servo updates to perform in a series event for hpoutl/hpoutr. 0 = 1 updates 1 = 2 updates ... 127 = 128 updates dc servo register 48h dc servo 5 register address bit label default description refer to r73 (49h) dc servo 6 7:0 dcs_dac_wr_ val_3 [7:0] 0000_0000 dc offset value for lineoutr in dac write dc servo mode in two's complement format. in readback, the current dc offset value is returned in two's complement format. two?s complement format: lsb is 0.25mv. range is +/-32mv dc servo register 49h dc servo 6
pre-production WM8904 w pp, rev 3.3, september 2012 163 register address bit label default description refer to r74 (4ah) dc servo 7 7:0 dcs_dac_wr_ val_2 [7:0] 0000_0000 dc offset value for lineoutl in dac write dc servo mode in two's complement format. in readback, the current dc offset value is returned in two's complement format. two?s complement format: lsb is 0.25mv. range is +/-32mv dc servo register 4ah dc servo 7 register address bit label default description refer to r75 (4bh) dc servo 8 7:0 dcs_dac_wr_ val_1 [7:0] 0000_0000 dc offset value for hpoutr in dac write dc servo mode in two's complement format. in readback, the current dc offset value is returned in two's complement format. two?s complement format: lsb is 0.25mv. range is +/-32mv dc servo register 4bh dc servo 8 register address bit label default description refer to r76 (4ch) dc servo 9 7:0 dcs_dac_wr_ val_0 [7:0] 0000_0000 dc offset value for hpoutl in dac write dc servo mode in two's complement format. in readback, the current dc offset value is returned in two's complement format. two?s complement format: lsb is 0.25mv. range is +/-32mv dc servo register 4ch dc servo 9 register address bit label default description refer to r77 (4dh) dc servo readback 0 11:8 dcs_cal_com plete [3:0] 0000 dc servo complete status [3] - lineoutr [2] - lineoutl [1] - hpoutr [0] - hpoutl 0 = dac write or start-up dc servo mode not completed. 1 = dac write or start-up dc servo mode complete. dc servo
WM8904 pre-production w pp, rev 3.3, september 2012 164 register address bit label default description refer to 7:4 dcs_dac_wr_ complete [3:0] 0000 dc servo dac write status [3] - lineoutr [2] - lineoutl [1] - hpoutr [0] - hpoutl 0 = dac write dc servo mode not completed. 1 = dac write dc servo mode complete. dc servo 3:0 dcs_startup _complete [3:0] 0000 dc servo start-up status [3] - lineoutr [2] - lineoutl [1] - hpoutr [0] - hpoutl 0 = start-up dc servo mode not completed.. 1 = start-up dc servo mode complete. dc servo register 4dh dc servo readback 0 register address bit label default description refer to r90 (5ah) analogue hp 0 7 hpl_rmv_sho rt 0 removes hpoutl short 0 = hpoutl short enabled 1 = hpoutl short removed for normal operation, this bit should be set as the final step of the hpl enable sequence. pop suppression control 6 hpl_ena_out p 0 enables hpoutl output stage 0 = disabled 1 = enabled for normal operation, this bit should be set to 1 after the dc offset cancellation has been scheduled. pop suppression control 5 hpl_ena_dly 0 enables hpoutl intermediate stage 0 = disabled 1 = enabled for normal operation, this bit should be set to 1 after the output signal path has been configured, and before dc offset cancellati on is scheduled. this bit should be set with at least 20us delay after hpl_ena. pop suppression control 4 hpl_ena 0 enables hpoutl input stage 0 = disabled 1 = enabled for normal operation, this bit should be set as the first step of the hpl enable sequence. pop suppression control 3 hpr_rmv_sho rt 0 removes hpoutr short 0 = hpoutr short enabled 1 = hpoutr short removed for normal operation, this bit should be set as the final step of the hpr enable sequence. pop suppression control 2 hpr_ena_out p 0 enables hpoutr output stage 0 = disabled 1 = enabled for normal operation, this bit should be set to 1 after the dc offset cancellation has been scheduled. pop suppression control
pre-production WM8904 w pp, rev 3.3, september 2012 165 register address bit label default description refer to 1 hpr_ena_dly 0 enables hpoutr intermediate stage 0 = disabled 1 = enabled for normal operation, this bit should be set to 1 after the output signal path has been configured, and before dc offset cancellati on is scheduled. this bit should be set with at least 20us delay after hpr_ena. pop suppression control 0 hpr_ena 0 enables hpoutr input stage 0 = disabled 1 = enabled for normal operation, this bit should be set as the first step of the hpr enable sequence. pop suppression control register 5ah analogue hp 0
WM8904 pre-production w pp, rev 3.3, september 2012 166 register address bit label default description refer to r94 (5eh) analogue lineout 0 7 lineoutl_rm v_short 0 removes lineoutl short 0 = lineoutl short enabled 1 = lineoutl short removed for normal operation, this bit should be set as the final step of the lineoutl enable sequence. pop suppression control 6 lineoutl_ena _outp 0 enables lineoutl output stage 0 = disabled 1 = enabled for normal operation, this bit should be set to 1 after the dc offset cancellation has been scheduled. pop suppression control 5 lineoutl_ena _dly 0 enables lineoutl intermediate stage 0 = disabled 1 = enabled for normal operation, this bit should be set to 1 after the output signal path has been configured, and before dc offset cancellati on is scheduled. this bit should be set with at least 20us delay after lineoutl_ena. pop suppression control 4 lineoutl_ena 0 enables lineoutl input stage 0 = disabled 1 = enabled for normal operation, this bit should be set as the first step of the lineoutl enable sequence. pop suppression control 3 lineoutr_rm v_short 0 removes lineoutr short 0 = lineoutr short enabled 1 = lineoutr short removed for normal operation, this bit should be set as the final step of the lineoutr enable sequence. pop suppression control 2 lineoutr_en a_outp 0 enables lineoutr output stage 0 = disabled 1 = enabled for normal operation, this bit should be set to 1 after the dc offset cancellation has been scheduled. pop suppression control 1 lineoutr_en a_dly 0 enables lineoutr intermediate stage 0 = disabled 1 = enabled for normal operation, this bit should be set to 1 after the output signal path has been configured, and before dc offset cancellati on is scheduled. this bit should be set with at least 20us delay after lineoutr_ena. pop suppression control 0 lineoutr_en a 0 enables lineoutr input stage 0 = disabled 1 = enabled for normal operation, this bit should be set as the first step of the lineoutr enable sequence. pop suppression control register 5eh analogue lineout 0
pre-production WM8904 w pp, rev 3.3, september 2012 167 register address bit label default description refer to r98 (62h) charge pump 0 0 cp_ena 0 enable charge-pump digits 0 = disable 1 = enable charge pump register 62h charge pump 0 register address bit label default description refer to r104 (68h) class w 0 cp_dyn_pwr 0 enable dynamic charge pump power control 0 = charge pump controlled by volume register settings (class g) 1 = charge pump controlled by real-time audio level (class w) class w is recommended for lowest power consumption. charge pump register 68h class w register address bit label default description refer to r108 (6ch) write sequencer 0 8 wseq_ena 0 write sequencer enable. 0 = disabled 1 = enabled control write sequencer 4:0 wseq_write_i ndex [4:0] 0_0000 sequence write index. this is the memory location to which any updates to r109 and r110 will be copied. 0 to 31 = ram addresses control write sequencer register 6ch write sequencer 0 register address bit label default description refer to r109 (6dh) write sequencer 1 14:12 wseq_data_ width [2:0] 000 width of the data block written in this sequence step. 000 = 1 bit 001 = 2 bits 010 = 3 bits 011 = 4 bits 100 = 5 bits 101 = 6 bits 110 = 7 bits 111 = 8 bits control write sequencer 11:8 wseq_data_s tart [3:0] 0000 bit position of the lsb of the data block written in this sequence step. 0000 = bit 0 ? 1111 = bit 15 control write sequencer 7:0 wseq_addr [7:0] 0000_0000 control register address to be written to in this sequence step. control write sequencer register 6dh write sequencer 1
WM8904 pre-production w pp, rev 3.3, september 2012 168 register address bit label default description refer to r110 (6eh) write sequencer 2 14 wseq_eos 0 end of sequence flag. this bit indicates whether the control write sequencer should stop after executing this step. 0 = not end of sequence 1 = end of sequence (stop the sequencer after this step). control write sequencer 11:8 wseq_delay [3:0] 0000 time delay after executing this step. total delay time per st ep (including execution)= 62.5s (2^wseq_delay + 8) control write sequencer 7:0 wseq_data [7:0] 0000_0000 data to be written in this sequence step. when the data width is less than 8 bits, then one or more of the msbs of wseq_data are ignored. it is recommended that unused bits be set to 0. control write sequencer register 6eh write sequencer 2 register address bit label default description refer to r111 (6fh) write sequencer 3 9 wseq_abort 0 writing a 1 to this bit aborts the current sequence and returns control of the device back to the serial control interface. control write sequencer 8 wseq_start 0 writing a 1 to this bit starts the write sequencer at the memory location indicated by the wseq_start_index field. the sequence continues until it reaches an ?end of sequence? flag. at the end of the sequence, this bit will be reset by the write sequencer. control write sequencer 5:0 wseq_start_ index [5:0] 00_0000 sequence start index. this is the memory location of the first command in the selected sequence. 0 to 31 = ram addresses 32 to 48 = rom addresses 49 to 63 = reserved control write sequencer register 6fh write sequencer 3 register address bit label default description refer to r112 (70h) write sequencer 4 9:4 wseq_curre nt_index [5:0] 00_0000 sequence current index (read only): this is the location of the most recently accessed command in the write sequencer memory. control write sequencer 0 wseq_busy 0 sequencer busy flag (read only): 0 = sequencer idle 1 = sequencer busy note: it is not possible to write to control registers via the control interface while the sequencer is busy. control write sequencer register 70h write sequencer 4
pre-production WM8904 w pp, rev 3.3, september 2012 169 register address bit label default description refer to r116 (74h) fll control 1 2 fll_fracn_e na 0 fll fractional enable 0 = integer mode 1 = fractional mode fractional mode (fll_fracn_ena=1) is recommended in all cases frequency locked loop (fll) 1 fll_osc_ena 0 fll oscillator enable 0 = disabled 1 = enabled fll_osc_ena must be enabled before enabling fll_ena. note that this field is required for free-running fll modes only. frequency locked loop (fll) 0 fll_ena 0 fll enable 0 = disabled 1 = enabled fll_osc_ena must be enabled before enabling fll_ena. frequency locked loop (fll) register 74h fll control 1 register address bit label default description refer to r117 (75h) fll control 2 13:8 fll_outdiv [5:0] 00_0000 fll fout clock divider 00_0000 = reserved 00_0001 = reserved 00_0010 = reserved 00_0011 = 4 00_0100 = 5 00_0101 = 6 ? 11_1110 = 63 11_1111 = 64 (fout = fvco / fll_outdiv) frequency locked loop (fll) 6:4 fll_ctrl_rat e [2:0] 000 frequency of the fll control block 000 = fvco / 1 (recommended value) 001 = fvco / 2 010 = fvco / 3 011 = fvco / 4 100 = fvco / 5 101 = fvco / 6 110 = fvco / 7 111 = fvco / 8 recommended that these are not changed from default. frequency locked loop (fll) 2:0 fll_fratio [2:0] 111 f vco clock divider 000 = divide by 1 001 = divide by 2 010 = divide by 4 011 = divide by 8 frequency locked loop (fll)
WM8904 pre-production w pp, rev 3.3, september 2012 170 register address bit label default description refer to 1xx = divide by 16 000 recommended for f ref > 1mhz 100 recommended for f ref < 64khz register 75h fll control 2 register address bit label default description refer to r118 (76h) fll control 3 15:0 fll_k [15:0] 0000_0000_0 000_0000 fractional multiply for fref (msb = 0.5) frequency locked loop (fll) register 76h fll control 3 register address bit label default description refer to r119 (77h) fll control 4 14:5 fll_n [9:0] 01_0111_0 111 integer multiply for fref (lsb = 1) frequency locked loop (fll) 3:0 fll_gain [3:0] 0000 fll gain applied to error 0000 = x 1 (recommended value) 0001 = x 2 0010 = x 4 0011 = x 8 0100 = x 16 0101 = x 32 0110 = x 64 0111 = x 128 1000 = x 256 recommended that these are not changed from default. frequency locked loop (fll) register 77h fll control 4 register address bit label default description refer to r120 (78h) fll control 5 4:3 fll_clk_ref_ div [1:0] 00 fll clock reference divider 00 = mclk / 1 01 = mclk / 2 10 = mclk / 4 11 = mclk / 8 mclk (or other input reference) must be divided down to <=13.5mhz. for lower power operation, the reference clock can be divided down further if desired. frequency locked loop (fll) 1:0 fll_clk_ref_ src [1:0] 00 fll clock source 00 = mclk 01 = bclk 10 = lrclk 11 = reserved frequency locked loop (fll) register 78h fll control 5
pre-production WM8904 w pp, rev 3.3, september 2012 171 register address bit label default description refer to r121 (79h) gpio control 1 5 gpio1_pu 0 gpio1 pull-up resistor enable 0 = pull-up disabled 1 = pull-up enabled general purpose input/output (gpio) 4 gpio1_pd 1 gpio1 pull-down resistor enable 0 = pull-down disabled 1 = pull-down enabled general purpose input/output (gpio) 3:0 gpio1_sel [3:0] 0100 gpio1 function select 0000 = input pin 0001 = clock output (f=sysclk/opclkdiv) 0010 = logic '0' 0011 = logic '1' 0100 = irq (default) 0101 = fll lock 0110 = mic detect 0111 = mic short 1000 = dmic clock out 1001 = fll clock output 1010 to 1111 = reserved general purpose input/output (gpio) register 79h gpio control 1 register address bit label default description refer to r122 (7ah) gpio control 2 5 gpio2_pu 0 gpio2 pull-up resistor enable 0 = pull-up disabled 1 = pull-up enabled general purpose input/output (gpio) 4 gpio2_pd 1 gpio2 pull-down resistor enable 0 = pull-down disabled 1 = pull-down enabled general purpose input/output (gpio) 3:0 gpio2_sel [3:0] 0000 gpio2 function select 0000 = input pin (default) 0001 = clock output (f=sysclk/opclkdiv) 0010 = logic '0' 0011 = logic '1' 0100 = irq 0101 = fll lock 0110 = mic detect 0111 = mic short 1000 = dmic clock out 1001 = fll clock output 1010 to 1111 = reserved general purpose input/output (gpio) register 7ah gpio control 2
WM8904 pre-production w pp, rev 3.3, september 2012 172 register address bit label default description refer to r123 (7bh) gpio control 3 5 gpio3_pu 0 gpio3 pull-up resistor enable 0 = pull-up disabled 1 = pull-up enabled general purpose input/output (gpio) 4 gpio3_pd 1 gpio3 pull-down resistor enable 0 = pull-down disabled 1 = pull-down enabled general purpose input/output (gpio) 3:0 gpio3_sel [3:0] 0000 gpio3 function select 0000 = input pin (default) 0001 = clock output (f=sysclk/opclkdiv) 0010 = logic '0' 0011 = logic '1' 0100 = irq 0101 = fll lock 0110 = mic detect 0111 = mic short 1000 = dmic clock out 1001 = fll clock output 1010 to 1111 = reserved general purpose input/output (gpio) register 7bh gpio control 3 register address bit label default description refer to r124 (7ch) gpio control 4 9 gpi7_ena 0 gpi7 input enable 0 = disabled 1 = enabled general purpose input/output (gpio) 8 gpi8_ena 0 gpi8 input enable 0 = disabled 1 = enabled general purpose input/output (gpio) 7 gpio_bclk_m ode_ena 0 selects bclk/gpio4 pin function 0 = bclk/gpio4 is used as bclk 1 = bclk/gpio4 is used as gpio. mclk provides the bclk in the aif in this mode. general purpose input/output (gpio) 3:0 gpio_bclk_se l [3:0] 0000 gpio_bclk function select: 0000 = input pin (default) 0001 = clock output (f=sysclk/opclkdiv) 0010 = logic '0' 0011 = logic '1' 0100 = irq 0101 = fll lock 0110 = mic detect 0111 = mic short 1000 = dmic clock out 1001 = fll clock output 1010 to 1111 = reserved general purpose input/output (gpio) register 7ch gpio control 4
pre-production WM8904 w pp, rev 3.3, september 2012 173 register address bit label default description refer to r126 (7eh) digital pulls 7 mclk_pu 0 mclk pull-up resistor enable 0 = pull-up disabled 1 = pull-up enabled digital audio interface control 6 mclk_pd 0 mclk pull-down resistor enable 0 = pull-down disabled 1 = pull-down enabled digital audio interface control 5 dacdat_pu 0 dacdat pull-up resistor enable 0 = pull-up disabled 1 = pull-up enabled digital audio interface control 4 dacdat_pd 0 dacdat pull-down resistor enable 0 = pull-down disabled 1 = pull-down enabled digital audio interface control 3 lrclk_pu 0 lrclk pull-up resistor enable 0 = pull-up disabled 1 = pull-up enabled digital audio interface control 2 lrclk_pd 0 lrclk pull-down resistor enable 0 = pull-down disabled 1 = pull-down enabled digital audio interface control 1 bclk_pu 0 bclk pull-up resistor enable 0 = pull-up disabled 1 = pull-up enabled digital audio interface control 0 bclk_pd 0 bclk pull-down resistor enable 0 = pull-down disabled 1 = pull-down enabled digital audio interface control register 7eh digital pulls register address bit label default description refer to r127 (7fh) interrupt status 10 irq 0 logical or of all other interrupt flags interrupts 9 gpio_bclk_ei nt 0 gpio4 interrupt 0 = interrupt not set 1 = interrupt is set cleared when a ?1? is written interrupts 8 wseq_eint 0 write sequence interrupt 0 = interrupt not set 1 = interrupt is set cleared when a ?1? is written. note that the read value of wseq_eint is not valid whilst the write sequencer is busy interrupts 7 gpio3_eint 0 gpio3 interrupt 0 = interrupt not set 1 = interrupt is set cleared when a ?1? is written interrupts 6 gpio2_eint 0 gpio2 interrupt 0 = interrupt not set 1 = interrupt is set cleared when a ?1? is written interrupts 5 gpio1_eint 0 gpio1 interrupt 0 = interrupt not set 1 = interrupt is set cleared when a ?1? is written interrupts
WM8904 pre-production w pp, rev 3.3, september 2012 174 register address bit label default description refer to 4 gpi8_eint 0 gpi8 interrupt 0 = interrupt not set 1 = interrupt is set cleared when a ?1? is written interrupts 3 gpi7_eint 0 gpi7 interrupt 0 = interrupt not set 1 = interrupt is set cleared when a ?1? is written interrupts 2 fll_lock_ein t 0 fll lock interrupt 0 = interrupt not set 1 = interrupt is set cleared when a ?1? is written interrupts 1 mic_shrt_ein t 0 micbias short circuit interrupt 0 = interrupt not set 1 = interrupt is set cleared when a ?1? is written interrupts 0 mic_det_eint 0 micbias current detect interrupt 0 = interrupt not set 1 = interrupt is set cleared when a ?1? is written interrupts register 7fh interrupt status register address bit label default description refer to r128 (80h) interrupt status mask 9 im_gpio_bclk _eint 1 gpio4 interrupt mask 0 = do not mask interrupt 1 = mask interrupt interrupts 8 im_wseq_eint 1 write sequencer interrupt mask 0 = do not mask interrupt 1 = mask interrupt interrupts 7 im_gpio3_eint 1 gpio3 interrupt mask 0 = do not mask interrupt 1 = mask interrupt interrupts 6 im_gpio2_eint 1 gpio2 interrupt mask 0 = do not mask interrupt 1 = mask interrupt interrupts 5 im_gpio1_eint 1 gpio1 interrupt mask 0 = do not mask interrupt 1 = mask interrupt interrupts 4 im_gpi8_eint 1 gpi8 interrupt mask 0 = do not mask interrupt 1 = mask interrupt interrupts 3 im_gpi7_eint 1 gpi7 interrupt mask 0 = do not mask interrupt 1 = mask interrupt interrupts 2 im_fll_lock_ eint 1 fll lock interrupt mask 0 = do not mask interrupt 1 = mask interrupt interrupts 1 im_mic_shrt_ eint 1 micbias short circuit interrupt mask 0 = do not mask interrupt 1 = mask interrupt interrupts 0 im_mic_det_ei 1 micbias current detect interrupt mask interrupts
pre-production WM8904 w pp, rev 3.3, september 2012 175 register address bit label default description refer to nt 0 = do not mask interrupt 1 = mask interrupt register 80h interrupt status mask register address bit label default description refer to r129 (81h) interrupt polarity 9 gpio_bclk_ei nt_pol 0 gpio4 interrupt polarity 0 = active high 1 = active low interrupts 8 wseq_eint_p ol 0 write sequencer interrupt polarity 0 = active high (interrupt is triggered when wseq is busy) 1 = active low (interrupt is triggered when wseq is idle) interrupts 7 gpio3_eint_p ol 0 gpio3 interrupt polarity 0 = active high 1 = active low interrupts 6 gpio2_eint_p ol 0 gpio2 interrupt polarity 0 = active high 1 = active low interrupts 5 gpio1_eint_p ol 0 gpio1 interrupt polarity 0 = active high 1 = active low interrupts 4 gpi8_eint_pol 0 gpi8 interrupt polarity 0 = active high 1 = active low interrupts 3 gpi7_eint_pol 0 gpi7 interrupt polarity 0 = active high 1 = active low interrupts 2 fll_lock_ein t_pol 0 fll lock interrupt polarity 0 = active high (interrupt is triggered when fll lock is reached) 1 = active low (interrupt is triggered when fll is not locked) interrupts 1 mic_shrt_ein t_pol 0 micbias short circuit interrupt polarity 0 = active high 1 = active low interrupts 0 mic_det_eint _pol 0 micbias current detect interrupt polarity 0 = active high 1 = active low interrupts register 81h interrupt polarity
WM8904 pre-production w pp, rev 3.3, september 2012 176 register address bit label default description refer to r130 (82h) interrupt debounce 9 gpio_bclk_ei nt_db 0 gpio4 interrupt debounce 0 = disabled 1 = enabled interrupts 8 wseq_eint_d b 0 write sequencer interrupt debounce enable 0 = disabled 1 = enabled interrupts 7 gpio3_eint_d b 0 gpio3 input debounce 0 = disabled 1 = enabled interrupts 6 gpio2_eint_d b 0 gpio2 input debounce 0 = disabled 1 = enabled interrupts 5 gpio1_eint_d b 0 gpio1 input debounce 0 = disabled 1 = enabled interrupts 4 gpi8_eint_db 0 gpi8 input debounce 0 = disabled 1 = enabled interrupts 3 gpi7_eint_db 0 gpi7 input debounce 0 = disabled 1 = enabled interrupts 2 fll_lock_ein t_db 0 fll lock debounce 0 = disabled 1 = enabled interrupts 1 mic_shrt_ein t_db 0 micbias short circuit interrupt debounce 0 = disabled 1 = enabled interrupts 0 mic_det_eint _db 0 micbias current detect interrupt debounce 0 = disabled 1 = enabled interrupts register 82h interrupt debounce register address bit label default description refer to r134 (86h) eq1 0 eq_ena 0 eq enable 0 = eq disabled 1 = eq enabled retune tm mobile parametric equalizer (eq) register 86h eq1 register address bit label default description refer to r135 (87h) eq2 4:0 eq_b1_gain [4:0] 0_1100 gain for eq band 1 00000 = -12db 00001 = -11db (? 1db steps) 01100 = 0db (? 1db steps) 11000 = +12db 11001 to 11111 = reserved retune tm mobile parametric equalizer (eq) register 87h eq2
pre-production WM8904 w pp, rev 3.3, september 2012 177 register address bit label default description refer to r136 (88h) eq3 4:0 eq_b2_gain [4:0] 0_1100 gain for eq band 2 00000 = -12db 00001 = -11db (? 1db steps) 01100 = 0db (? 1db steps) 11000 = +12db 11001 to 11111 = reserved retune tm mobile parametric equalizer (eq) register 88h eq3 register address bit label default description refer to r137 (89h) eq4 4:0 eq_b3_gain [4:0] 0_1100 gain for eq band 3 00000 = -12db 00001 = -11db (? 1db steps) 01100 = 0db (? 1db steps) 11000 = +12db 11001 to 11111 = reserved retune tm mobile parametric equalizer (eq) register 89h eq4 register address bit label default description refer to r138 (8ah) eq5 4:0 eq_b4_gain [4:0] 0_1100 gain for eq band 4 00000 = -12db 00001 = -11db (? 1db steps) 01100 = 0db (? 1db steps) 11000 = +12db 11001 to 11111 = reserved retune tm mobile parametric equalizer (eq) register 8ah eq5 register address bit label default description refer to r139 (8bh) eq6 4:0 eq_b5_gain [4:0] 0_1100 gain for eq band5 00000 = -12db 00001 = -11db (? 1db steps) 01100 = 0db (? 1db steps) 11000 = +12db 11001 to 11111 = reserved retune tm mobile parametric equalizer (eq) register 8bh eq6
WM8904 pre-production w pp, rev 3.3, september 2012 178 register address bit label default description refer to r140 (8ch) eq7 15:0 eq_b1_a [15:0] 0000_1111_1 100_1010 eq band 1 coefficient a retune tm mobile parametric equalizer (eq) register 8ch eq7 register address bit label default description refer to r141 (8dh) eq8 15:0 eq_b1_b [15:0] 0000_0100_ 0000_0000 eq band 1 coefficient b retune tm mobile parametric equalizer (eq) register 8dh eq8 register address bit label default description refer to r142 (8eh) eq9 15:0 eq_b1_pg [15:0] 0000_0000_1 101_1000 eq band 1 coefficient pg retune tm mobile parametric equalizer (eq) register 8eh eq9 register address bit label default description refer to r143 (8fh) eq10 15:0 eq_b2_a [15:0] 0001_1110_1 011_0101 eq band 2 coefficient a retune tm mobile parametric equalizer (eq) register 8fh eq10 register address bit label default description refer to r144 (90h) eq11 15:0 eq_b2_b [15:0] 1111_0001_0 100_0101 eq band 2 coefficient b retune tm mobile parametric equalizer (eq) register 90h eq11 register address bit label default description refer to r145 (91h) eq12 15:0 eq_b2_c [15:0] 0000_1011_0 111_0101 eq band 2 coefficient c retune tm mobile parametric equalizer (eq) register 91h eq12 register address bit label default description refer to r146 (92h) eq13 15:0 eq_b2_pg [15:0] 0000_0001_1 100_0101 eq band 2 coefficient pg retune tm mobile parametric equalizer (eq) register 92h eq13 register address bit label default description refer to r147 (93h) eq14 15:0 eq_b3_a [15:0] 0001_1100_0 101_1000 eq band 3 coefficient a retune tm mobile parametric equalizer (eq) register 93h eq14
pre-production WM8904 w pp, rev 3.3, september 2012 179 register address bit label default description refer to r148 (94h) eq15 15:0 eq_b3_b [15:0] 1111_0011_0 111_0011 eq band 3 coefficient b retune tm mobile parametric equalizer (eq) register 94h eq15 register address bit label default description refer to r149 (95h) eq16 15:0 eq_b3_c [15:0] 0000_1010_0 101_0100 eq band 3 coefficient c retune tm mobile parametric equalizer (eq) register 95h eq16 register address bit label default description refer to r150 (96h) eq17 15:0 eq_b3_pg [15:0] 0000_0101_0 101_1000 eq band 3 coefficient pg retune tm mobile parametric equalizer (eq) register 96h eq17 register address bit label default description refer to r151 (97h) eq18 15:0 eq_b4_a [15:0] 0001_0110_1 000_1110 eq band 4 coefficient a retune tm mobile parametric equalizer (eq) register 97h eq18 register address bit label default description refer to r152 (98h) eq19 15:0 eq_b4_b [15:0] 1111_1000_0 010_1001 eq band 4 coefficient b retune tm mobile parametric equalizer (eq) register 98h eq19 register address bit label default description refer to r153 (99h) eq20 15:0 eq_b4_c [15:0] 0000_0111_1 010_1101 eq band 4 coefficient c retune tm mobile parametric equalizer (eq) register 99h eq20 register address bit label default description refer to r154 (9ah) eq21 15:0 eq_b4_pg [15:0] 0001_0001_0 000_0011 eq band 4 coefficient pg retune tm mobile parametric equalizer (eq) register 9ah eq21 register address bit label default description refer to r155 (9bh) eq22 15:0 eq_b5_a [15:0] 0000_0101_0 110_0100 eq band 5 coefficient a retune tm mobile parametric equalizer (eq) register 9bh eq22
WM8904 pre-production w pp, rev 3.3, september 2012 180 register address bit label default description refer to r156 (9ch) eq23 15:0 eq_b5_b [15:0] 0000_0101_0 101_1001 eq band 1 coefficient b retune tm mobile parametric equalizer (eq) register 9ch eq23 register address bit label default description refer to r157 (9dh) eq24 15:0 eq_b5_pg [15:0] 0100_0000_0 000_0000 eq band 5 coefficient pg retune tm mobile parametric equalizer (eq) register 9dh eq24 register address bit label default description refer to r198 (c6h) adc test 0 2 adc_128_os r_tst_mode 0 adc bias control (1) set this bit to 1 in adc 64fs mode (adc_osr128 = 0). set this bit to 0 in adc 128fs mode (adc_osr128 = 1). adc oversampling ratio (osr) 0 adc_biasx1p 5 0 adc bias control (2) set this bit to 1 in adc 64fs mode (adc_osr128 = 0). set this bit to 0 in adc 128fs mode (adc_osr128 = 1). adc oversampling ratio (osr) register c6h adc test 0 register address bit label default description refer to r247 (f7h) fll nco test 0 0 fll_frc_nc o 0 fll forced control select 0 = normal 1 = fll oscillator controlled by fll_frc_nco_val (note that this field is required for free-running fll modes only) frequency locked loop (fll) register f7h fll nco test 0 register address bit label default description refer to r248 (f8h) fll nco test 1 5:0 fll_frc_nc o_val [5:0] 01_1001 fll forced oscillator value valid range is 000000 to 111111 0x19h (011001) = 12mhz approx (note that this field is required for free-running fll modes only) frequency locked loop (fll) register f8h fll nco test 1
pre-production WM8904 w pp, rev 3.3, september 2012 181 applications information recommended external components figure 71 recommended external components notes: 1. decoupling capacitors x5r ceramic capacitor is recommended for capacitors c1, c2, c3, c4, c5, c15, c16, c17 and c18. the positioning of c17 and c18 is very important - these should be as close to the WM8904 as possible. capacitors c15 and c16 should also be positioned as close to the WM8904 as possible. 2. charge pump capacitors specific recommendations for c14, c15 and c16 are provided in table 95. note that two different recommendations are provided for c15 and c16; either of these components is suitable, depending upon size requirements and availability. the positioning of c14 is very important - this should be as close to the WM8904 as possible. it is important to select a suitable capacitor type for the c harge pump. note that the capacitance may vary with dc voltage; care is required to ensure that required capacitance is achieved at t he applicable operating voltage, as specified in table 95. the capacitor datasheet should be c onsulted for this information. component required capacitance value part number voltage type size c14 (cpca-cpcb) ? 1? f at 2vdc 2.2 ? f kemet c0402c225m9pac 6.3v x5r 0402 c15 (cpvoutn) c16 (cpvoutp) ? 2? f at 2vdc 2.2? f murata grm188r61a225ke34d 10v x5r 0603 4.7? f murata grm155r60j475m_eia 6.3v x5r 0402 table 95 charge pump capacitors
WM8904 pre-production w pp, rev 3.3, september 2012 182 3. zobel networks the zobel network shown in figure 71 is required on hpoutl, hpoutr, lineoutl and lineoutr whenever that output is enabled. stability of these ground-referenced outputs across a ll process corners cannot be guaranteed without the zobel network components. (note that, if any ground-referenced output pin is not required, the zobel network components can be omitted from the output pin, and the pin can be left floating.) the zobel network requirement is detailed further in the applications note wan_0212 ?class w headphone impedance compensation?. zobel networks (c6, c7, c8, c9, r1, r2, r3, r4 ) should be positioned reasonabl y close to the WM8904. 4. microphone grounding r7 and r8 can be populated with other values to re move common mode noise on the microphone if required.
pre-production WM8904 w pp, rev 3.3, september 2012 183 mic detection sequence using micbias current this section details an example sequence which su mmarises how the host processor can configure and detect the events supported by the micbias cu rrent detect function (see ?electret condenser microphone interface?): ? mic insertion/removal ? hook switch press/release figure 72 shows an example of how the micbias cu rrent flow varies versus time, during mic insertion and hook switch events. the y axis is annotated with the mic detection thresholds, and the x axis is annotated with the stages of an example s equence as detailed in table 96, to illustrate how the host processor can implement mic insertion and hook switch detection. the sequence assumes that the microphone insert ion and hook switch detection functions are monitored by polling the interrupt fl ags using the control interface. no te that the maximum mechanical bounce times for mic insertion and removal must be fully understood by the software programmer. a gpio pin could be used as an al ternative mechanism to monitor the micbias detection functions. this enables the host processor to detect mechanical bounce at any time. time mic hook switch threshold mic detect interrupt micbias current (1) (2) (4) (5) (6) (7) (8) (9) t det t det mic detect threshold hysteresis (3) (10) t short t short mic detect interrupt polarity mic short interrupt mic short interrupt polarity mic_det_eint mic_det_eint_pol mic_shrt_eint mic_shrt_eint_pol host processor read the mic detect interrupt flag. if high, can then set mic_det_eint_pol to 1, but only if mechanical bounce phase has finished. clear mic_det_eint by writing ?1?. read the hook switch interrupt flag. if high, can immediately set mic_shrt_eint_pol to 1. clear mic_shrt_eint by writing ?1?. read the hook switch interrupt flag. if high, can immediately clear mic_shrt_eint_pol to 0. clear mic_shrt_eint by writing ?1?. read the mic detect interrupt flag. if high, can then clear mic_det_eint_pol to 0, but only if mechanical bounce phase has finished. clear mic_det_eint by writing ?1?. step (1) (2) (4) (5) (6) (7) (8) (9) (3) (10) step example plot of micbias current versus time mic inserted hook switch pressed figure 72 mic insert and hook switch detect: example micbias current plot
WM8904 pre-production w pp, rev 3.3, september 2012 184 step details 1 mic not inserted. to detect mic insertion, host processor mu st initialise interrupts and clear mic_det_eint_pol = 0. at every step, the host processor should poll the interrupt status register. note that mic insertion de-bounce circuitry can be enabled by setting mic_det_eint_db = 1. 2 mechanical bounce of jack socket during mic insertion. host processor may already detect a mic insertion interrupt (mic_det_eint) during this step. once detected, the hos t processor can set mic_det_eint_pol = 1 and then clear the interrupt, unless mechanical bounce can la st longer than the shortest possible t det , in which case the host processor should wait until step 3. 3 mic fully inserted. if not already set, the host processor mu st now set mic_det_eint_pol = 1. if not already cleared, the host processor must now clear the mic_det_eint interrup t. to detect hook switch press, the host processor must clear mic_shrt_eint_pol = 0. at this step, the diagram s hows no ac current swing, due to a very low ambient noise level. 4 mic fully inserted. diagram shows ac current swing due to high levels of background noise (such as wind). 5 mechanical bounce during hook switch press. the hook switch in terrupt is unlikely to be set during this step, because 10 successive samples of the micbias current exceeding the hook switch threshold have not yet been sampled. note that hook switch de-bounce circuitry c an be enabled by setting mic_shrt_eint_db = 1. 6 hook switch is fully pressed down. after t short , 10 successive samples of the micbias current exceeding the hook switch threshold have been detected, hence a hook switch interrupt (mic_shrt_eint) will be generated. once detected, the host processor can immediately set mi c_shrt_eint_pol = 1 and then clear the mic_shrt_eint interrupt. 7 mechanical bounce during hook switch release. the hook switch interrupt is unlikely to be set during this step, because 10 successive samples of the micbias current lower than the hook switch threshold have not yet been sampled. 8 hook switch fully released. after t short , 10 successive samples of the micbias current lower than the hook switch threshold have been detected, hence a hook switch interrupt (mic_shrt_eint) will be generated. once detected, the host processor can immediately clear mic_shrt_eint_pol = 0 and then clear the mic_shrt_eint interrupt. 9 mechanical bounce of jack socket during mic removal. host processor may already detect a mic removal interrupt (mic_det_eint) during this step. once detected, the hos t processor can clear mic_det_eint_pol = 0 and then clear the interrupt, unless mechanical bounce can la st longer than the shortest possible t det , in which case the host processor should wait until step 10. 10 mic fully removed. if not already cleared, the host processo r must now clear mic_det_eint_pol = 0. if not already cleared, the host processor must now clear the mic_det_eint interrupt. table 96 mic insert and hook switch detect: example sequence alternatively, utilising a gpio pin to monitor the micbias current detect functionality permits the host processor to monitor the steady state of mi crophone detection or hook switch press functions. because the gpio shows the steady state conditi on, software de-bounce may be easier to implement in the host processor, dependant on the processor performance characterist ics, hence use of the gpio is likely to simplify the rejection of mec hanical bounce. changes of state in the gpio pin are also subject to the time delays t det and t short .
pre-production WM8904 w pp, rev 3.3, september 2012 185 package dimensions the 36-ball w-csp package drawing is shown below. b: 36 ball w-csp package 2.651 x 2.525 x 0.698mm body, 0.40 mm ball pitch a1 corner top view e a aaa 2 x d 5 4 detail 2 detail 2 a a2 2 b aaa 2 x a1 z bbb z 1 e1 a d1 detail 1 d c b f e e e bottom view 1 65 432 g notes: 1. primary datum -z- and seating plane are defined by the spherical crowns of the solder balls. 2. this dimension includes stand-off height ?a1? and backside coating. 3. a1 corner is identified by ink/laser mark on top package. 4. bilateral tolerance zone is applied to each side of the package body. 5. ?e? represents the basic solder ball grid pitch. 6. this drawing is subject to change without notice. 7. follows jedec design guide mo-211-c. a1 0.177 d d1 e e1 e 2.000 bsc 2.525 0.313 2.000 bsc 0.400 bsc 2.651 dimensions (mm) symbols min nom max note a 0.698 a2 0.452 0.468 0.484 5 f1 0.733 0.663 0.208 0.239 g 0.022 h 0.258 f2 0.250 f1 f2 h dm066.c 2.626 2.676 2.500 2.550 0.218 0.298 4 a b z ddd m a b z ccc aaa bbb ccc ddd 0.025 0.060 0.030 0.015 detail 1
WM8904 pre-production w pp, rev 3.3, september 2012 186 the 32-pin qfn package drawing is shown below. fl: 32 pin qfn plastic package 4 x 4 x 0.75 mm body, 0.40 mm lead pitch e2 b b 15 a 8 9 e c 0.08 c ccc a a1 c a3 seating plane 1 l index area (d/2 x e/2) top view d c aaa 2 x c aaa 2 x e 1 17 24 25 32 d2 bc bbb m a 5 4 notes: 1. dimension b applies to metallized terminal and is measured between 0.15 mm and 0.25 mm from terminal tip. 2. all dimensions are in millimetres. 3. the terminal #1 identifier and terminal numbering convention shall conform to jedec 95-1 spp-002. 4. coplanarity applies to the exposed heat sink slug as well as the terminals. 5. refer to application note wan_ 0118 for furt her information regarding pcb footprints and qfn package soldering. 6. this drawing is subject to change without notice. a3 g b exposed lead detail 1 detail 1 exposed ground paddle 6 bottom view side view 16 dm067.a dimensions (mm) symbols min nom max note a a1 a3 0.70 0.75 0.8 0.05 0.035 0 0.203 ref b d d2 e e2 e l 0.25 0.15 4.00 bsc 2.75 2.7 2.65 0.40 bsc 0.35 0.40 0.45 1 2 2 4.00 bsc 2.75 2.7 2.65 0.10 aaa bbb ccc ref: 0.05 0.10 tolerances of form and position 0.2 0.5 g
pre-production WM8904 w pp, rev 3.3, september 2012 187 important notice wolfson microelectronics plc (?wol fson?) products and services are sold subject to wolfson?s terms and conditions of sale, delivery and payment supplied at the time of order acknowledgement. wolfson warrants performance of its products to the specifications in effect at t he date of shipment. wolfson reserves the right to make changes to its products and s pecifications or to discontinue any product or service without notice. customers should therefore obtain the latest version of relevant information from wolfson to verify that the information is current. testing and other quality control techniques are utilised to the extent wolfson deems necessary to support its warranty. specific testing of all parameters of each device is not necessarily performed unless requi red by law or regulation. in order to minimise risks associated with customer app lications, the customer must use adequate design and operating safeguards to minimise inherent or proc edural hazards. wolfson is not liable fo r applications assistance or customer product design. the customer is solely responsible for its se lection and use of wolfson products . wolfson is not liable for such selection or use nor for use of any circuitry other than circuitry entirely embodied in a wolfson product. wolfson?s products are not intended for use in life support systems, appliances, nuclear systems or systems where malfunction can reasonably be expected to re sult in personal injury, death or severe property or environmental damage. any use of products by the customer for such purposes is at the customer?s own risk. wolfson does not grant any licence (express or implied) under any patent right, copyright, mask work right or other intellectual property right of wolfson covering or relating to any combination, machine, or pr ocess in which its products or services might be or are used. any prov ision or publication of any third party?s products or services does not constitute wolfson?s approval, licence, warranty or endorsement thereof. any third party trade marks contained in this document belong to the respective third party owner. reproduction of information from wolfson datasheets is per missible only if reproduction is without alteration and is accompanied by all associated copyright, proprietary and other not ices (including this notice) and conditions. wolfson is not liable for any unauthorised alteration of such in formation or for any reliance placed thereon. any representations made, warranties giv en, and/or liabilities accepted by any pers on which differ from those contained in this datasheet or in wolfson?s standard terms and conditions of sale, delivery and payment are made, given and/or accepted at that person?s own risk. wolfson is not liable for any such representations, warranties or liabilities or for any reliance placed thereon by any person. address wolfson microelectronics plc westfield house 26 westfield road edinburgh eh11 2qb tel :: +44 (0)131 272 7000 fax :: +44 (0)131 272 7001 email :: sales@wolfsonmicro.com
WM8904 pre-production w pp, rev 3.3, september 2012 188 revision history date rev description of changes page changed by 05/08/11 3.3 low power playback mode definition and characteristics added. isel (bias control) register added 22,23,81, 82,142 ph 10/01/12 3.3 order codes updated to WM8904cgefl/v and WM8904cgefl/rv to reflect change to copper wire bonding 8 jmacd 24/08/12 3.3 36 ball package diagram updated to dm066.c 185 jmacd 27/08/12 3.3 headline dac to headphone playback power consumption updated to 3.0mw. 1 ssaunders 03/09/12 3.3 w-csp reel quantity changed to 5,000 1 jmacd

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